Experience

Alstom Brasil Energia e Transporte Ltda.

• Brazil
• Machinery Manufacturing
• 1 - 100 Employee

• Industrial Coordinator

  • Apr 2018 - Present

  Management of supplier activities. Interface between engineering and industrial suppliers. Guarantee of production, quality and deliveries. Industrial KPIs Line balance , tools development PCBa process correspondent IPC-A-610, lean, 6 sigma Management of supplier activities. Interface between engineering and industrial suppliers. Guarantee of production, quality and deliveries. Industrial KPIs Line balance , tools development PCBa process correspondent IPC-A-610, lean, 6 sigma



Alstom Brasil Energia e Transporte LTDA

• Brazil
• Machinery Manufacturing
• 1 - 100 Employee

• PCB expert

  • Aug 2004 - Nov 2021

  PCB designer, placement&route, back end, gerber files, assembly drawingEDA tools manangement .DFM, DFT and DFQ application, PCBa consulting.SAFETY PCB, analog design AC/AF, Digital Signal Processor, QFP, QFN, BGA MentorGraphics tools BoardStation Expedition Hyperlinx Modelsim PCAD 7 , Altium PCAD, EN50121 EN50155 EN50129 IPC2221 IPC2222 IPC-SM-782 IPC-A-600Hardware Process CorrespondentUnix Solaris environment and Windows MWEshared work with France USA and Italy

• Program Manager

  • Apr 2014 - Mar 2021

  Drive Development programsManagement of schedule planning and control, cost control, QCD achievement



Instituto de Pesquisas Eldorado

• Brazil
• IT Services and IT Consulting
• 700 & Above Employee

• intern

  • 2004 - 2004

  CDMA and GSM phone SW configuration CDMA and GSM phone SW configuration



Centro BioInformatica Embrapa

• IT manager

  • Feb 2003 - Oct 2003

  Network management and maintenance . Sun and SGI Unix (Irix Solaris ) , Linux , winNT , Cluster . Network management and maintenance . Sun and SGI Unix (Irix Solaris ) , Linux , winNT , Cluster .



Freescale Semiconductor

• V & V designer

  • Jan 2002 - Dec 2002

  Verilog design for testbench and regression tools 32 bit uP test and validation SoC design RTL , Synthesis , pattern conversion , back end simulation Cadence Verilog , Synopsys Verilog design for testbench and regression tools 32 bit uP test and validation SoC design RTL , Synthesis , pattern conversion , back end simulation Cadence Verilog , Synopsys



Promon Tecnologia

• Manufacturing

• Hardware Engineer

  • 1998 - 2001

  PCB designer for telecommunications multi-procesor E1/T1 systems , VoIP and MGCP devices librarian , front end tools with MentorGraphics Board Station Reliability calculation RELEX Unix Solaris environment PCB designer for telecommunications multi-procesor E1/T1 systems , VoIP and MGCP devices librarian , front end tools with MentorGraphics Board Station Reliability calculation RELEX Unix Solaris environment



CenPRA

• Research Services
• 1 - 100 Employee

• Application-Specific Integrated Circuit Designer

  • Apr 1996 - Jan 1998

  Develop ASIC, CPLD and FPGA designs with logic, VHDL IC creation, IC Station , Altera MaxPlus Quartus Xlinx ISE Unix Solaris environment Develop ASIC, CPLD and FPGA designs with logic, VHDL IC creation, IC Station , Altera MaxPlus Quartus Xlinx ISE Unix Solaris environment