Experience

CEA-List
• France
• Think Tanks
• 100 - 200 Employee
• INGENIEUR CHERCHEUR-VERIFICATION / MODÉLISATION ET NUMÉRIQUE

  • Nov 2021 - Present


STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• Functional IP Verification

  • Apr 2016 - May 2022

  Working on DDR subsystems (LPDDR3, LPDDR4, DDR3, DDR4...) verification in the context of asics for spacial or automotive SoCVerification based on SystemVerilog UVM and also Jasper for formal verification of some specifics aspects.

• IP Security Functionnal Verification

  • Jan 2015 - Apr 2016

  Working the verification of the Security IPs of different SET TOP BOX

• SoC Team Leader and Object Leader

  • Sep 2013 - Jan 2015

  Working on an ASIC addressing the gaming market.



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Project management: Design Verification Object Leader at ST-Ericsson

  • Dec 2009 - Sep 2013

  Project management for chips used in Tablets and Smartphones: Design Verification Object Leader: 1) SOC IPs verification Object Leader: Responsible for the verification of SOC IPs (Memory Controller, Interconnect, Display Controller, Clock Generator...) for all the projects - Up to 10 SOC IPs in parallel - Up to 5 projects in parallel - Up to 15 people, located in France, Finland, China, Morocco, India, to manage 2) SOC verification Object Leader: Responsible for the verification of one SOC => very challenging project (Company's Priority) - Around 40 people, located in France, Finland and Morocco, to manage Show less

• Verification Engineer

  • Mar 2008 - Dec 2009

  1) Low power verification at SOC level (45 nm): C-testcases & PSL assertions 2) Functional IP verification of System Controller (Clocks, resets, Interrupts and Low power sequences controls): Coverage Driven Verification based on Specman 3) IP verification Coordinator: Coordination of up to 15 IP verification activities done, by new comers, on other IP verification teams 1) Low power verification at SOC level (45 nm): C-testcases & PSL assertions 2) Functional IP verification of System Controller (Clocks, resets, Interrupts and Low power sequences controls): Coverage Driven Verification based on Specman 3) IP verification Coordinator: Coordination of up to 15 IP verification activities done, by new comers, on other IP verification teams



PSI Electronics

• Semiconductors
• 1 - 100 Employee

• Verification Engineer

  • Sep 2006 - Feb 2008

  Functional verification of SOC IPs: 1) Memory Controller: Coverage Driven verification based on Specman 2) Flow controller: - SoC Level : Directed C-testcases & system tests generator (PERL) developments - IP level: eVC (Specman eRM) development Functional verification of SOC IPs: 1) Memory Controller: Coverage Driven verification based on Specman 2) Flow controller: - SoC Level : Directed C-testcases & system tests generator (PERL) developments - IP level: eVC (Specman eRM) development