Lhoucine Said

Senior IC Design Verification Engineer at Rianta Solutions Inc.
  • Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Location
Kanata, Ontario, Canada, CA
Languages
  • 1-Tamazight Native or bilingual proficiency
  • 2-Arabic Professional working proficiency
  • 3-French Professional working proficiency
  • 4-English Professional working proficiency

Topline Score

Bio

Generated by
Topline AI

0

/5.0
/ Based on 0 ratings
  • (0)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

No reviews to display There are currently no reviews available.

0

/5.0
/ Based on 0 ratings
  • (0)
  • (0)
  • (0)
  • (0)
  • (0)

Filter reviews by:

No reviews to display There are currently no reviews available.
You need to have a working account to view this content. Click here to join now

Experience

  • Rianta Solutions Inc.
    • Canada
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Senior IC Design Verification Engineer
      • Jun 2014 - Present

      Design Verification: - UVM, SystemVerilog, - Data Center, DMA, Pcie, AXI, APB, I2C- Test Plans,- Build Testbench (UVM),- Test Plan Execution and Debug,- Regressions,- Coverage Closure,- Performance- Block level and full chip.

  • Freescale Semiconductor
    • Senior IC Design Verification Engineer
      • Oct 2012 - May 2014

      Design Verification: - VMM Like environment, SystemVerilog, - Packet Fifo Management, AXI, - Test Plans,- Build Testbench,- Test Plan Execution and Debug,- Regressions,- Coverage Closure,

  • XtremeEda Corporation
    • United States
    • Principal Asic Verification Consultant
      • Mar 2012 - Aug 2012

      ASIC Verification

  • Exar Corporation
    • United States
    • Semiconductor Manufacturing
    • 100 - 200 Employee
    • Software Development, ASIC Verification Engineer
      • Jun 2009 - Feb 2012

      Design Verification:- FPGA design and lab validation,- 10G OTN/SONET/SDH Multi-Service Mapper and Multiplexer,- SystemVerilog, C++, DPI/PLI,- Test Plans,- Build Testbench,- Test Plan Execution and Debug,- Regressions,

  • Galazar Networks Inc.
    • Software Engineer (drivers and lab validation)
      • May 2006 - Feb 2010

    • ASIC Verification/Design
      • Jun 2003 - May 2006

  • Aquilo Technologies
    • IT Services and IT Consulting
    • 1 - 100 Employee
    • Design Verification
      • Dec 2000 - Jun 2003

      Design verification and protocol modeling

  • Agere Systems
    • Design Verification
      • Dec 1999 - Nov 2000

      Design verification and protocol modeling

  • Lucent Technologies
    • United States
    • Telecommunications
    • 200 - 300 Employee
    • Design Verification
      • Jul 1999 - Dec 1999

      Design verification and protocol modeling

  • Nortel Networks
    • Telecommunications
    • 700 & Above Employee
    • Lab Validation Engineer
      • Aug 1997 - Jul 1999

      Lab validation

  • Maroc Telecom
    • Morocco
    • Telecommunications
    • 700 & Above Employee
    • Network Maintenance
      • Jan 1994 - Dec 1996

      Network maintenance

Education

  • École Nationale Supérieure des Télécommunications de Bretagne
    -
  • INPT (Institut National des Postes et Télécommunications)
    -
  • Université Cadi Ayyad Marrakech
    -

Community

You need to have a working account to view this content. Click here to join now