Experience

Fundación Fulgor

• Argentina
• Higher Education
• 1 - 100 Employee

• Master Degree Student in Autonomous Navigation

  • May 2020 - Present



Inphi Corporation

• United States
• Semiconductor Manufacturing
• 100 - 200 Employee

• Senior Design Engineer

  • Oct 2016 - May 2020

  I worked on design, implementation and verification of ASIC hardware modules in RTL for different projects using C++, Python, Verilog. These modules are related to Digital Signal Processing, Forward Error Correction and Framer projects. I worked on design, implementation and verification of ASIC hardware modules in RTL for different projects using C++, Python, Verilog. These modules are related to Digital Signal Processing, Forward Error Correction and Framer projects.



ClariPhy Communications

• United States
• Semiconductors
• 1 - 100 Employee

• Junior Engineering

  • Sep 2015 - Oct 2016

  I worked a year on Digital Signal Processing doing design, implementation and verification of hardware modules in RTL for M200 project. I worked a year on Digital Signal Processing doing design, implementation and verification of hardware modules in RTL for M200 project.



In Bio

• Intern

  • Feb 2011 - Dec 2011

  I worked on the design and implementation of biomedical projects. I designed a histological sample processor and this project won an award in a technology conference at Tecnópolis. I worked on the design and implementation of biomedical projects. I designed a histological sample processor and this project won an award in a technology conference at Tecnópolis.