Laurentiu Popa
Digital Verification Engineer at TTTech- Claim this Profile
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Bio
Experience
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TTTech
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Austria
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Computer Networking Products
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200 - 300 Employee
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Digital Verification Engineer
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Mar 2019 - Present
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Digital Verification Engineer
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Sep 2017 - Feb 2019
Functional verification of IPs targeting Automotive and Industrial markets with focus on Time Sensitive Networking. Developing both verification infrastructure ( SV / UVM and VHDL/ OSVVM environments) as well as testcases.
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EASYIC DESIGN
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Romania
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Semiconductors
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1 - 100 Employee
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Verification Engineer
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Jun 2015 - Aug 2017
System level verification tasks in UVM for ARM. Software driven test cases and IP level UVM testing. System level verification tasks in UVM for ARM. Software driven test cases and IP level UVM testing.
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TTTech
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Austria
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Computer Networking Products
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200 - 300 Employee
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FPGA / ASIC design Engineer
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Nov 2012 - Jun 2015
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Heitec AG
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Germany
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Automation Machinery Manufacturing
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100 - 200 Employee
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FPGA Design Engineer
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Nov 2010 - Nov 2012
- Elaboration of Concept Studies Chapters and Functional Specification Chapters for various proprietary hardware modules and RTL IP cores. - Understanding requirements/specifications of various projects that need a hardware implementation on FPGA and proposing required architecture solutions. - Implementation, verification (behavioral, timing analysis, laboratory testing) and debugging of the proposed architectures . Applications on Xilinx Virtex6 and Virtex7/Kintex devices. - Managing verification environment in Python and TCL - C firmware test scenarios and procedures for embedded RTOS. - Debugging of known issues in close contact with the company clients, both in-house and onsite. Show less
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Infineon Technologies
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Germany
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Semiconductor Manufacturing
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700 & Above Employee
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Digital Design Intern
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Sep 2009 - Jun 2010
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