Experience

NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Principal Engineer

  • Feb 2006 - Present

  Team-lead for back-end work (synthesis, multi-voltage timing closure, layout, netlist verification, and methodology development) on 5nm graphics processing units (GPU) for gaming, data centers, computer vision, deep-learning (DL), and artificial intelligence (AI), plus the ARM-compatible line of Tegra SoC/CPU ASICs as inference engines for autonomous (self-driving) vehicles. Team-lead for back-end work (synthesis, multi-voltage timing closure, layout, netlist verification, and methodology development) on 5nm graphics processing units (GPU) for gaming, data centers, computer vision, deep-learning (DL), and artificial intelligence (AI), plus the ARM-compatible line of Tegra SoC/CPU ASICs as inference engines for autonomous (self-driving) vehicles.



NEC Electronics

• Japan
• Semiconductors
• 100 - 200 Employee

• Principal Engineer

  • Sep 2002 - Jan 2006

  Application of Dynamically Reconfigurable Processors (DRPs) to ASIC design. ASIC Place-and-Route (P&R) using Magma tool suite. Dynamic IR-drop analysis using Apache Redhawk tools. Technical support to Sales and Marketing. Application of Dynamically Reconfigurable Processors (DRPs) to ASIC design. ASIC Place-and-Route (P&R) using Magma tool suite. Dynamic IR-drop analysis using Apache Redhawk tools. Technical support to Sales and Marketing.



Vitesse Semiconductor is now Microsemi

• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Design Engineer

  • Dec 1999 - Jul 2002

  Back-end timing closure on ASICs for ATM traffic management. World-wide chair person for the SPI-4 Working Group. Back-end timing closure on ASICs for ATM traffic management. World-wide chair person for the SPI-4 Working Group.



Raleigh Technology Corp.

• HW Manager

  • May 1999 - Dec 1999

  Managing a team of ASIC HW Engineers for designing survivable-ring ethernet chipsets. Managing a team of ASIC HW Engineers for designing survivable-ring ethernet chipsets.



Nortel Networks

• Telecommunications
• 700 & Above Employee

• Senior Design Engineer

  • Aug 1989 - May 1999

  ASIC designer for central-office telecommunications equipment. Verilog coding, synthesis, back-end timing closure. Development of JTAG boundary-scan macros for design-for-testability (DFT). Developing 1850 MHz RF low-noise base-station amplifiers (LNAs) using in-house GaAs MESFET process. Developing 10 GHz travelling-wave/distributed amplifiers to drive optical modulators, using in-house InGaAsP HBT process. Mask/stepper-tile layout. ASIC designer for central-office telecommunications equipment. Verilog coding, synthesis, back-end timing closure. Development of JTAG boundary-scan macros for design-for-testability (DFT). Developing 1850 MHz RF low-noise base-station amplifiers (LNAs) using in-house GaAs MESFET process. Developing 10 GHz travelling-wave/distributed amplifiers to drive optical modulators, using in-house InGaAsP HBT process. Mask/stepper-tile layout.



Nortel Networks

• Senior Engineer

  • 1989 - 1999



Computing Devices Company

• Senior Design Engineer

  • Mar 1986 - Aug 1989

  Militarization of CRAY super-computer HW for sonar and synthetic aperature radar (SAR). Systems engineer for integrating remotely piloted air drones onto naval frigates. Militarization of CRAY super-computer HW for sonar and synthetic aperature radar (SAR). Systems engineer for integrating remotely piloted air drones onto naval frigates.



Canadian Marconi Company

• Design Engineer

  • May 1983 - Mar 1986

  Design and develop Viterbi decoders. Integrate militarized PBX equipment into packet-switched radio networks. Develop real-time operating system (RTOS) firmware for frequency hopping radio. Machine-coding of binomial decomposition for prediction of 89-bit pseudo-random polynomials. Design and develop Viterbi decoders. Integrate militarized PBX equipment into packet-switched radio networks. Develop real-time operating system (RTOS) firmware for frequency hopping radio. Machine-coding of binomial decomposition for prediction of 89-bit pseudo-random polynomials.



Governor General's Foot Guards

• Ottawa, Ontario, Canada

• Corporal

  • May 1980 - Oct 1984

  Training instructor. Training instructor.