Design Engineer

• Jun 2018 - Present

AMS Verification Engineer - Contract

• Apr 2020 - Present

* Worked on full chip verification of Neuron Chip.* Setting up Verification TB at Top Level for blocks like ADCs / DACs / GPIOs* Verification TB for various modes of operation for the ASIC including Reading/Writing/Training modes.* Digital Logic Verification/ Characterization for ASIC for Controls driving the Analog.* Verification of DFF, Latches, Level Shifters, MUX, IOs for Setup Time / Hold Time / Delay / Power.* Power Down Implementation / Verification of ASIC for Block… * Worked on full chip verification of Neuron Chip.* Setting up Verification TB at Top Level for blocks like ADCs / DACs / GPIOs* Verification TB for various modes of operation for the ASIC including Reading/Writing/Training modes.* Digital Logic Verification/ Characterization for ASIC for Controls driving the Analog.* Verification of DFF, Latches, Level Shifters, MUX, IOs for Setup Time / Hold Time / Delay / Power.* Power Down Implementation / Verification of ASIC for Block wise Powerdown / FSM Generation for PowerDown modes. Show more Show less

Memory Design Engineer Subcon

• Sep 2018 - Apr 2020

* Worked on low power Memory compiler Design / Verification for 40nm tech.* Skilled in Bitcell Analysis / Margin Analysis.* Responsible for PPA Checks for Compiler Release for important parameters like Power, Delay, Risetime, Falltime etc.* Worked over Write Assist Methodology for improving Write Performance.* Worked over Characterization flow / Timing checks at Memory Compiler level.* Verification for Setup / Hold / Duty Cycle/ Min Pulse width requirement for complex… * Worked on low power Memory compiler Design / Verification for 40nm tech.* Skilled in Bitcell Analysis / Margin Analysis.* Responsible for PPA Checks for Compiler Release for important parameters like Power, Delay, Risetime, Falltime etc.* Worked over Write Assist Methodology for improving Write Performance.* Worked over Characterization flow / Timing checks at Memory Compiler level.* Verification for Setup / Hold / Duty Cycle/ Min Pulse width requirement for complex Sequential Circuit designs for Memory Compilers.* Worked on Critical Path Methodology for Memory Compilers. Show more Show less

Design Verification Engineer Subcon

• Jul 2018 - Sep 2018

Worked on Verification of GPIOs. Created test benches for measuring VOH, VOL , Iave through IO pads. IBIS methodology. Modification of existing verification flow to verify the entire GPIO for Spec Doc.

Undergraduate Research Award (UGRA)

• Sep 2017 - Jun 2018

UGRA is a prestigious research Program offered by Department of Physics and Computer Science, Dayalbagh Educational institute under which students are promoted and motivated to persue research in their field of expertise for a period of 9 months which results in a paper publication later on.

Summer Training

• May 2016 - Jul 2016