Experience

Rianta Solutions Inc.

• Canada
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Staff Design Engineer

  • Dec 2019 - Present

  Designed, implemented, and maintained L2 and simplified L3/L4 ethernet parser and extractor.

• Staff Design Engineer

  • Oct 2017 - Dec 2019

  Architected and implemented ARM CPU subsystem comprised of ARM Cortex A35 CPU coupled with ARM CoreSight SoC-400 debug and trace components as well as ARM CoreLink GIC-500 interrupt controller.• Designed and generated ARM CoreSight SoC-400 subsystem using ARM Socrates tools to create debug subsystem to satisfy customer specifications• Instantiated and tested memories for all components including A35 CPU and ETB within CoreSight SoC-400• Implemented an adapter between AMBA AXI4 and ROM memory in order to connect CPU boot ROM to NIC-400 interconnect• Instantiated various support modules for the CPU subsystem including CPU Generic Timer and Watchdog timer• Wrote programs using C and Assembly that were executed on the A35 CPU during RTL simulation to help verify functionality and performance of the CPU in the system• Setup and ran Real Intent lint and Synopsys Spyglass CDC to identify and fix any issues design issues• Designed and implemented fuse controller to connect to existing chip infrastructure and to meet customer requirements



Istuary IoT Labs

• Senior ASIC Design Engineer

  • Oct 2016 - Sep 2017

  Architected and implemented the bus structure comprised of many components including CPU, AHB and APB buses, radio, and memory as well as architected power distribution network including DC-DC regulators, LDOs, POR, and BOR for the Istuary IoT System-On-Chip (SoC). • Led team of design engineers in implementation and integration of in-house IPs as well as integration of 3rd party IPs into the SoC • Designed and implemented power management unit to control power domains with retention flip flops while having minimal dynamic power consumption • Defined power islands in such a way as to minimize the SoC power consumption during standby and sleep modes • Configured and integrated many 3rd party peripheral IPs including I2C, and SPI peripherals into the SoC • Worked with various IP suppliers to define, develop and customize various digital and mixed signal IPs required for the SoC • Closely collaborated with verification team including test plan reviews and testing methodology definition • Setup and ran Synopsys Spyglass lint as well as defined a methodology for the design team to follow. • Setup Xilinx VCU110 FPGA platform to emulate a custom Verilog module • Collaborated with PCB board design team to create an extension card for a Xilinx FPGA board containing various mixed signal chips to emulate the full functionality of the SoC



Qualcomm

• United States
• Telecommunications
• 700 & Above Employee

• Senior Digital Hardware Designer

  • May 2012 - Apr 2016

  • Designed and implemented various internal components for Standalone Memory Management Unit (SMMU) such as fault response logic and write reorder buffer using Verilog, which improved SMMU performance up to 10% • Simulated the designs using VCS and ModelSim to minimize number of bugs before delivering to the DV team • Updated, supported, and maintained general purpose FIFOs and AHB2AHB Bridges used inside large number of chips all across the Qualcomm IP portfolio • Setup, executed, and debugged many flows such as Atrenta Spyglass, Synopsis DC, and 0in CDC for SMMU, FIFOs, and AHB2AHB Bridges • Designed an automated flow using Perl to generate top level Verilog wrappers based on parameters extracted from *.xls spreadsheets, which reduced designer time contribution by 90% • Created Verilog memory wrapper program using Perl to assemble memories necessary for the RTL design, eliminating the previously required manual work for the task completion • Synthesized the SMMU design into hardened macro, and worked with the back end teams (PD) to address layout and timing issues • Received two recognition awards (Qualstars) for excellent work on the SMMU



University of Toronto Blue Sky Solar Racing

• Electrical System Team Lead

  • May 2010 - Oct 2013

  • Designed circuit schematics based on Atmel’s AT91SAM and Microchip’s PIC18 microcontrollers for “Azure” and “B-7” solar vehicles, reduced power consumption by 20% compared to the previous generations • Created PCB layout for both power distribution and telemetry system using Altium Designer with the focus on minimizing the board area • Generated Bill of Materials (BOM) for all schematics and worked with various vendors to acquire all required electronic components • Soldered and verified electrical circuits using multimeter and Tektronix oscilloscope • Designed, implemented and installed the entire power train system including battery box layout for both solar vehicles • Managed and guided team members through electrical design and construction of the solar vehicles up until the completion of the vehicles • Participated in 2011 & 2013 World Solar Challenge in Australia and achieved 8th place out of 23 teams from around the world



AMD

• France
• Architecture and Planning
• 1 - 100 Employee

• ASIC Design Engineer

  • May 2010 - Sep 2011

  • Implemented RTL module to deterministically synchronize signals between multiple clock domains using Verilog • Designed and implemented multiple automated RTL checkers using Verilog and C++, to ensure correct functionality of RTL modules • Synthesized multiple chip tiles using Cadence RTL compiler • Designed constraints and timing analysis of multiple chip tiles • Ran RTL verification tools including 0in CDC, Synopsys Leda, and Synopsys Formality • Implemented a number of scripts to automate tasks using Perl