Experience

Startup

• Semiconductor Manufacturing
• 400 - 500 Employee

• Design Engineer

  • Nov 2021 - Present

  Contributed in power optimization of a core designResponsible for RTL design in high performance CPU cores Contributed in power optimization of a core designResponsible for RTL design in high performance CPU cores



Lampró Méllon

• Pakistan
• Technology, Information and Internet
• 1 - 100 Employee

• Associate Design Engineer

  • Jan 2020 - Oct 2021

  Part of a team responsible for designing of low speed peripheral IPs,Worked in a team for integrating internal design with Caravel SoC for Efabless Open MPW Shuttle Program,Developed Continuous Gap Analysis System for benchmarking of FPGA tools,Designed a DCache to integrate it with SweRV EH2 Core Part of a team responsible for designing of low speed peripheral IPs,Worked in a team for integrating internal design with Caravel SoC for Efabless Open MPW Shuttle Program,Developed Continuous Gap Analysis System for benchmarking of FPGA tools,Designed a DCache to integrate it with SweRV EH2 Core