Experience

ATLAS ELEKTRONIK UK

• United Kingdom
• Defense and Space Manufacturing
• 200 - 300 Employee

• FPGA Verification Engineer

  • Sep 2018 - Present



Taotek Ltd

• United Kingdom
• Semiconductor Manufacturing

• Director, Lead Consultant

  • Aug 2013 - Present

  Hardware and Software Consultancy Hardware and Software Consultancy



L3 TRL Technology

• Tewksbury

• Consultant FPGA Engineer

  • Sep 2017 - Apr 2018



Viasat

• United States
• Telecommunications
• 700 & Above Employee

• Firmware Verification Engineer

  • Jun 2015 - May 2017

  System Verilog testbench for product firmware IP and VHDL module design and test. System Verilog testbench for product firmware IP and VHDL module design and test.



Red Bee Media

• Broadcast Media Production and Distribution
• 700 & Above Employee

• Contract FPGA Design & Verification Consultant

  • Jul 2014 - Feb 2015

  Verification using system verilog and UVM. Verification using system verilog and UVM.



Korusys Ltd

• United Kingdom
• Semiconductor Manufacturing
• 1 - 100 Employee

• Verification Consultant

  • Sep 2013 - Jul 2014

  Verification of HEVC FPGA IP using verilog, system verilog and systemC. Verification of HEVC FPGA IP using verilog, system verilog and systemC.



Roke

• United Kingdom
• IT Services and IT Consulting
• 400 - 500 Employee

• Consultant Engineer

  • Jul 1997 - Jul 2013

  One of the key VHDL engineers at Roke involved in all aspects of VHDL develoment from requirements through design to verification. Involved with defining and advancing the VHDL/FPGA/ASIC development process and good design practices using code coverage, defined CDC schemes, requirements tracing, etc. As well as VHDL/FPGA experience I have software skills covering system specification, UML, C++, C, Python through the complete software development cycle. Software platforms include UNIX variants, Windows and embedded systems (processors/DSP with and without RTOS). Used various tools and different flavours such as configuration management (clearcase, SVN), IDE's, debuggers, logic analyzers, etc whatever is needed to get the job done. Every project at Roke seems to need different skills and tools so I have a wide range of skills with varying expertise (and sometimes needs a decent prompt to remember!). I've team led projects, done bid work and ensured quality in both hw and sw roles. %age on SW skilled projects has been approx 60%, FPGA/VHDL projects 30% and the remaining on bid and process work. Show less



University of Southampton

• United Kingdom
• Higher Education
• 700 & Above Employee

• Research and Teaching Fellow

  • Oct 1995 - Jul 1997

  Taught C structures. Course work. Support and help with other research students.

• Research Fellow

  • Oct 1992 - Oct 1995

  DTI/SERC ASSET project and in also extensions to the MOODS sythesis tool. ELLA to VHDL parser.

• Research Assistant

  • Oct 1989 - Sep 1992

  PhD and DTI funded work. "ELLA Behavioural Synthesis" with DRA and Plessey.Created the MOODS (Multiple Objective Optimisation of control and Data Path Synthesis) synthesis system. This spawned a number of other reseach projects in the department.The first tool to automatically explore the design space in the area, power, and speed space by the application of complex behavioural optimisations.