Kazi Shady
Engineer L3, ASIC PD at PrimeSilicon Technology (BD) Ltd.- Claim this Profile
Click to upgrade to our gold package
for the full feature experience.
Topline Score
Bio
0
/5.0 / Based on 0 ratingsFilter reviews by:
Experience
-
PrimeSilicon Technology (BD) Ltd.
-
Bangladesh
-
Appliances, Electrical, and Electronics Manufacturing
-
1 - 100 Employee
-
Engineer L3, ASIC PD
-
Jul 2022 - Present
¬ Conducting block-level floorplanning, power planning, CTS, and routing tasks.¬ Developing a pre-route script for IP (GPIOs).¬ Developing custom pg mash script for PLL, VQPS, and eFUSE.¬ Utilizing STA, Calibre DRC, and Formality for block-level design.¬ Providing training to junior engineers on handling fusion compiler tools.¬ Offering feedback to the RTL, DFT, and SDC teams.
-
-
ASIC Design Implementation Engineer
-
Jul 2019 - Jun 2022
¬ Conducting block-level floorplanning, power planning, CTS, and routing tasks. ¬ Developing SDC for block-level design.¬ Performing EMIR, STA, PV, and LEC analysis for block-level design.¬ Providing feedback to the RTL and DFT team. ¬ Worke as a supporting Engineer
-
-
Junior ASIC Design Engineer
-
Apr 2018 - Jun 2019
¬ Working on 14 nm technology, I have experience in custom scripting and PnR tasks on ICC2 ¬ Hands-on experience in supporting 7 nm and 14 nm processes using ICC2 Compiler ¬ Proficient knowledge of design import, floorplanning, cell placement, and macro placement in both 7nm and 14nm processes. ¬ Physical verification techniques such as DRC, LVS, ERC, and antenna checks, as well as IR/EM/Xtalk reliability checks. ¬ Writing Tcl scripts to customize the clock tree for high-speed blocks. ¬ Ability to independently run small projects using Synopsys ICC2 ¬ Practical understanding of timing report analysis and debugging of timing-related issues Show less
-
-
Physical Design Engineer (Intern)
-
Oct 2017 - Mar 2018
-
-
Education
-
United International University
Bachelor's degree, Electrical and Electronics Engineering