Software Engineer

• Apr 2019 - Present

PROFINET Test System Development PROFINET Test System Development

Embedded Software Engineer

• Mar 2018 - Mar 2019

• Developing simulation environment for the features like Wheel auto location(WAL) and Phase auto location(PAL) of TPMS software development • Writing simulation test cases in C language on CodeWarrior, implementing simulation automation for continuous integration with Jenkins • Adding new features and resolving the bugs in the software, Programming and debugging the TPMS sensors with Cyclone pro debugger tools • Preparing test-plans for simulation, emulation and vehicle testing for the complete validation process of TPMS sensors

Master Thesis Student

• Jan 2017 - Jul 2017

• Implemented and integrated AHB transaction checker, UART modules with LEON3 processor by using ISE design suite 14.7 with VHDL • Established synchronized serial communication between the host computer and the nexys 3 spartan-6 FPGA board • Programmed the LEON3 processor to examine the timing results from the hardware and the SoCRocket TLM model with different benchmarks written in C language • Implemented and integrated AHB transaction checker, UART modules with LEON3 processor by using ISE design suite 14.7 with VHDL • Established synchronized serial communication between the host computer and the nexys 3 spartan-6 FPGA board • Programmed the LEON3 processor to examine the timing results from the hardware and the SoCRocket TLM model with different benchmarks written in C language

student

• 2014 - 2017

Student assistent

• Jul 2016 - Dec 2016

Ageing analysis of a RISC-Processor based on different stress profiles: --The signal probability of the different sub-circuit of an OpenRISC processor(OR1200) has been analyzed. --Implemented automated test benches in verilog for toggle rate analysis of different sub-circuit of OR1200 processor. Ageing analysis of a RISC-Processor based on different stress profiles: --The signal probability of the different sub-circuit of an OpenRISC processor(OR1200) has been analyzed. --Implemented automated test benches in verilog for toggle rate analysis of different sub-circuit of OR1200 processor.

Student Worker

• Jul 2015 - Sep 2015