Karnitski Anton

Senior Analog IC Designer at Pacific Microchip Corp.
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Contact Information
us****@****om
(386) 825-5501
Location
Los Angeles, California, United States, US
Languages
  • English Professional working proficiency
  • Russian Native or bilingual proficiency
  • Belarusian Native or bilingual proficiency
Skills

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Credentials

  • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features v19.1 Exam
    Cadence Design Systems
    Jun, 2021
    - Sep, 2024
  • Quantus Transistor-Level T1: Overview and Technology Setup v19.1 Exam
    Cadence Design Systems
    Sep, 2020
    - Sep, 2024

Experience

  • Pacific Microchip Corp.
    • United States
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Senior Analog IC Designer
      • Jan 2017 - Present

      Design 5GHz 24-phase output Multi-Phase Clock Generator in 16nm TSMC FinFET Design 8-bit 56GS/s Time-Interleaved ADC in 28nm TSMC CMOS Design 32 channel 12-bit 500MS/s Low Latency ADC array ASIC in 28nm TSMC CMOS Design 32 channel 12-bit 200MS/s ADC array ASIC in 28nm TSMC CMOS with Event-Driven Gigital Backend Design 4 Chanel 20Gs/s 2-bit Correlation Radiometer ASIC in 28nm TSMC CMOS Design Radiation hardened General Purpose Controller ASIC in 65nm Jazz Design 5GHz 24-phase output Multi-Phase Clock Generator in 16nm TSMC FinFET Design 8-bit 56GS/s Time-Interleaved ADC in 28nm TSMC CMOS Design 32 channel 12-bit 500MS/s Low Latency ADC array ASIC in 28nm TSMC CMOS Design 32 channel 12-bit 200MS/s ADC array ASIC in 28nm TSMC CMOS with Event-Driven Gigital Backend Design 4 Chanel 20Gs/s 2-bit Correlation Radiometer ASIC in 28nm TSMC CMOS Design Radiation hardened General Purpose Controller ASIC in 65nm Jazz

  • GateSilicon
    • United States
    • Non-profit Organizations
    • 1 - 100 Employee
    • RF Analog IC design
      • Apr 2013 - Jan 2017

      Design and testing of high speed ADC converter in TSMC 28nm CMOS (Time interleaved 56GS/s 8bit) Design and testing of high speed DAC converter in GF 28nm CMOS (64GS/s 8bit); Design of transimpedance amplifier (TIA) 28Gbit in SiGe BiCMOS; Design and testing of RF transmitter; Behavior modeling analog sub-systems using VerilogA and mixed-mode modeling using Verilog functional; Design and testing of high speed ADC converter in TSMC 28nm CMOS (Time interleaved 56GS/s 8bit) Design and testing of high speed DAC converter in GF 28nm CMOS (64GS/s 8bit); Design of transimpedance amplifier (TIA) 28Gbit in SiGe BiCMOS; Design and testing of RF transmitter; Behavior modeling analog sub-systems using VerilogA and mixed-mode modeling using Verilog functional;

  • NTLab
    • Lithuania
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • RF Analog IC design
      • Sep 2008 - Apr 2013

      Analog RF IC designer. Design and testing of PLL frequency synthesizers: Integer-N and Fractional-N frequency synthesizers in CMOS/BiCMOS processes (TSMC, SMIC, iHP, AMS); Design frequency synthesizers auxiliary circuits: low dropout voltage regulators, bandgap voltage reference, simple SAR/Flash-ADC, frequency buffers. Behavior modeling analog sub-systems using VerilogA and mixed-mode modeling using Verilog functional; Using high speed/low power logic styles; Analog RF IC designer. Design and testing of PLL frequency synthesizers: Integer-N and Fractional-N frequency synthesizers in CMOS/BiCMOS processes (TSMC, SMIC, iHP, AMS); Design frequency synthesizers auxiliary circuits: low dropout voltage regulators, bandgap voltage reference, simple SAR/Flash-ADC, frequency buffers. Behavior modeling analog sub-systems using VerilogA and mixed-mode modeling using Verilog functional; Using high speed/low power logic styles;

Education

  • Belarusian State University of Informatics and Radioelectronics
    Bachelor's Degree, Micro- and Nanoelectronic Technologies and Systems
    2005 - 2008
  • Minsk State Higher Radioengineering College
    Department, specialization “Technology of integral microchips”, qualification - Technician-technolog, Microelectronics
    2001 - 2005
  • 63
    High School
    1992 - 2001

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