Juan Heredia
Communications System Engineer at Telesat- Claim this Profile
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Spanish Native or bilingual proficiency
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English Full professional proficiency
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Português Full professional proficiency
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Bio
Experience
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Telesat
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Canada
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Telecommunications
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300 - 400 Employee
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Communications System Engineer
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Mar 2020 - Present
- Design and verification GEO satellite link budgets - Matlab modelling of satellite impairments - STK modeling of Lightspeed satellite constellation to find elevation/LoS obstructions with customer landing sites - Design and verification GEO satellite link budgets - Matlab modelling of satellite impairments - STK modeling of Lightspeed satellite constellation to find elevation/LoS obstructions with customer landing sites
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Microsemi Corporation
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Semiconductor Manufacturing
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700 & Above Employee
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Graduate Research Student
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2016 - 2019
Work Experience: • Created a MATLAB phase noise analyzer tool/model for three separate PLL products to be used by Nokia for verification • Designed GUI for phase noise analyzer tool to improve client testing experience • Conducted design meetings to discuss model-product inconsistencies to improve phase noise analyzer tool • Developed phase noise test plans to ensure the efficacy of marketed features • Tested PLL products in the lab through the use of TCL Scripts designed to read and write registers Thesis: • Successfully implemented MATLAB behavioral model of an All-Digital Phased-Locked Loop fabricated at Microsemi • Conducted TIE analysis of ADPLL to illustrate the model’s filter characteristics • Collaborated in the design of a novel Filter-to-DCO frequency decoder • Preformed runtime analysis of MATLAB behavioural model to further improve simulation speed Show less
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COVELOZ Technologies Inc.
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Canada
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Broadcast Media Production and Distribution
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1 - 100 Employee
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Hardware Validation and Software Engineer
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May 2014 - Aug 2015
Worked closely with FPGA engineers to debug and test their audio networking solutions: • Designed VHDL block to test the regression path of a MADI system • Implemented TCL based script to create hierarchical register paths of internal projects • Migrated FPGA design using Qsys to a new target board increasing companies’ available products Worked closely with FPGA engineers to debug and test their audio networking solutions: • Designed VHDL block to test the regression path of a MADI system • Implemented TCL based script to create hierarchical register paths of internal projects • Migrated FPGA design using Qsys to a new target board increasing companies’ available products
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Carleton University
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Higher Education
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700 & Above Employee
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NSERC Research Student
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May 2013 - Aug 2014
• Adapted and operated a fiber to fiber optical alignment set-up for research purposes • Conducted insertion loss measurements of fiber to fiber connection at an optimal position to proceed with polarizing experiments • Utilized LabVIEW to control movements of an optical alignment set-up • Adapted and operated a fiber to fiber optical alignment set-up for research purposes • Conducted insertion loss measurements of fiber to fiber connection at an optimal position to proceed with polarizing experiments • Utilized LabVIEW to control movements of an optical alignment set-up
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Carleton University
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Higher Education
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700 & Above Employee
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Engineering Research Assistant
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May 2012 - Aug 2012
Constructed a tablet size infrared LED touch-screen that can be used as an input device Constructed a tablet size infrared LED touch-screen that can be used as an input device
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Education
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Carleton University
Master of Applied Science (M.A.Sc), Electrical and Electronics Engineering -
Carleton University
Bachelor of Engineering (B.Eng.), Electrical and Electronics Engineering -
St. Joseph Highschool
Diploma, Highschool