Juan Heredia

Communications System Engineer at Telesat
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Contact Information
us****@****om
(386) 825-5501
Location
Ottawa, Ontario, Canada, CA
Languages
  • Spanish Native or bilingual proficiency
  • English Full professional proficiency
  • Português Full professional proficiency

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Experience

    • Canada
    • Telecommunications
    • 300 - 400 Employee
    • Communications System Engineer
      • Mar 2020 - Present

      - Design and verification GEO satellite link budgets - Matlab modelling of satellite impairments - STK modeling of Lightspeed satellite constellation to find elevation/LoS obstructions with customer landing sites - Design and verification GEO satellite link budgets - Matlab modelling of satellite impairments - STK modeling of Lightspeed satellite constellation to find elevation/LoS obstructions with customer landing sites

    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Graduate Research Student
      • 2016 - 2019

      Work Experience: • Created a MATLAB phase noise analyzer tool/model for three separate PLL products to be used by Nokia for verification • Designed GUI for phase noise analyzer tool to improve client testing experience • Conducted design meetings to discuss model-product inconsistencies to improve phase noise analyzer tool • Developed phase noise test plans to ensure the efficacy of marketed features • Tested PLL products in the lab through the use of TCL Scripts designed to read and write registers Thesis: • Successfully implemented MATLAB behavioral model of an All-Digital Phased-Locked Loop fabricated at Microsemi • Conducted TIE analysis of ADPLL to illustrate the model’s filter characteristics • Collaborated in the design of a novel Filter-to-DCO frequency decoder • Preformed runtime analysis of MATLAB behavioural model to further improve simulation speed Show less

    • Canada
    • Broadcast Media Production and Distribution
    • 1 - 100 Employee
    • Hardware Validation and Software Engineer
      • May 2014 - Aug 2015

      Worked closely with FPGA engineers to debug and test their audio networking solutions: • Designed VHDL block to test the regression path of a MADI system • Implemented TCL based script to create hierarchical register paths of internal projects • Migrated FPGA design using Qsys to a new target board increasing companies’ available products Worked closely with FPGA engineers to debug and test their audio networking solutions: • Designed VHDL block to test the regression path of a MADI system • Implemented TCL based script to create hierarchical register paths of internal projects • Migrated FPGA design using Qsys to a new target board increasing companies’ available products

    • Higher Education
    • 700 & Above Employee
    • NSERC Research Student
      • May 2013 - Aug 2014

      • Adapted and operated a fiber to fiber optical alignment set-up for research purposes • Conducted insertion loss measurements of fiber to fiber connection at an optimal position to proceed with polarizing experiments • Utilized LabVIEW to control movements of an optical alignment set-up • Adapted and operated a fiber to fiber optical alignment set-up for research purposes • Conducted insertion loss measurements of fiber to fiber connection at an optimal position to proceed with polarizing experiments • Utilized LabVIEW to control movements of an optical alignment set-up

    • Higher Education
    • 700 & Above Employee
    • Engineering Research Assistant
      • May 2012 - Aug 2012

      Constructed a tablet size infrared LED touch-screen that can be used as an input device Constructed a tablet size infrared LED touch-screen that can be used as an input device

Education

  • Carleton University
    Master of Applied Science (M.A.Sc), Electrical and Electronics Engineering
    2016 - 2019
  • Carleton University
    Bachelor of Engineering (B.Eng.), Electrical and Electronics Engineering
    2011 - 2016
  • St. Joseph Highschool
    Diploma, Highschool
    2005 - 2011

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