Experience

Nanya Technology

• Taiwan
• Semiconductors
• 300 - 400 Employee

• Senior Design Engineer

  • Jun 2020 - Present



Self-employed

• Available

  • Feb 2020 - Jun 2020



Marvell Technology

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Staff Analog Design Engineer

  • Nov 2019 - Feb 2020

  Technical lead for SERDES development in the TSMC N7 node. Analog and overall team leadership for execution of a 112Gbps XSR Serdes Technical lead for SERDES development in the TSMC N7 node. Analog and overall team leadership for execution of a 112Gbps XSR Serdes



Global Foundries / Avera Semiconductor

• Principal Member Of Technical Staff

  • Jul 2015 - Nov 2019

  Analog Technical lead for SERDES Development in the Global Foundries 14LPP and 7LP technologies as well as the TSMC N7 process. Analog and overall team leadership for 30G Gbps, 60G Gbps and 112 Gbps SERDES cores. Analog Technical lead for SERDES Development in the Global Foundries 14LPP and 7LP technologies as well as the TSMC N7 process. Analog and overall team leadership for 30G Gbps, 60G Gbps and 112 Gbps SERDES cores.



IBM

• United States
• IT Services and IT Consulting
• 700 & Above Employee

• Senior Development Engineer, Analog & Mixed Signal Cores

  • Apr 1999 - Jun 2015

  Analog Team Lead for 32nm SOI Low Power HMC 15 Gbps USR SERDES; Responsible for technical leadership of an international engineering team responsible for developing a low power USR interface compatible with the HMC specification, analog component architecture, circuit design leadership and design delivery.Design of high frequency clock distribution, redundancy logic and data strobe / synchronization functions for use in a 64 Gbps Interleaved ADC-based SERDES including circuit-level design, physical floorplanning of the multi-ADC slice, interconnect modeling and post-physical design verification.Analog Team Lead for 22nm SOI DDR3 / DDR4 Physical Layer; Responsible for technical leadership of a multi-site team developing DDR3 / DDR4 interfaces to specific customer-driven functional and power requirements. Directly responsible for architectural and circuit definition for multiple analog sub-components including DACs, references, regulators, receiver and driver circuits and delay lines as well as oversight of the physical design, customer interface and design delivery / release.Team Lead for a thirty-plus member team tasked with rapid turn-around diagnosis and correction of functionality issues with 3rd Party IP purchased by a key 65nm bulk foundry customer. Maintained direct interface to both the customer and the IP provider and directed the team in a comprehensive diagnostic effort which resulted in extensive recommendations for design update, on-schedule design re-submission and functional hardware.Design lead for reference, linear regulator and power-on indicator functions servicing both higher-level mixed-signal functions and ASIC library offerings in the 120nm, 90nm and 65nm bulk technology nodes as well as the 45nm SOI technology node.Lead engineer for Ethernet physical layer core design and integration into IBM ASIC's 90nm node

• Development Engineer

  • Jan 1990 - Apr 1999

  Design Lead for Ethernet physical layer core design and integration into IBM ASIC's 90nm node offeringLead Engineer for development of a field-programmable memory array product providing flexible / reconfigurable RAM, Register, LIFO and FIFO functionality to IBM's fine grain FPGA architecture.Lead design for the ASIC library development in 0.5um technologies.Design of compilable random access memories and register arrays for ASIC applications

• Product Assurance Engineer

  • Nov 1984 - Dec 1989

  Verification and qualification of IBM custom and ASIC product offerings in depleted NMOS and first / second generation CMOS technologies including verification of circuit behavioral and timing models, electrical specifications, physical design tooling and reliability performance.