Staff Engineer

• Apr 2021 - Present

Embedded Software/FPGA Engineer

• Apr 2019 - Mar 2021

Development of devices for Train Communication and Control. My responsibilities include: Firmware development (Verilog. VHDL and C/C++) and formal verification of IP Cores. • Product R&D, implementing customer requirements, debugging (both HW and SW) and testing. • Experience in communication protocols such as PCI, PCI-Express, USB, MVB and Ethernet. Programming in Real-Time OS environments. • Experience in contributing and collaboratively maintaining a very large code base, of both FPGA IP Cores and Software, in a team of 50+ people, using Git. • Experience in using CI/CD platforms, such as Gitlab and Jenkins. • Technical support to the Sales and Application Teams Show less

Electronics Engineer - Fellowship Programme

• Sep 2016 - Jan 2019

R&D Engineering Team of the lpGBT Project, a multi-gigabit, radiation-hard transceiver for communications between the front-end sensors and counting room. My responsibilities included: • Theoretical study, simulation and RTL implementation of a Reed-Solomon Forward Error Correction Codec for multi-gigabit links. • Collaboration in the development of the FPGA testing board for the ASIC, based on a Virtex7 core. My work used GTX Transceivers, ISERDES/OSERDES, PLLs and other specialised FPGA blocks. • Full-chip verification environment development using UVM/SystemVerilog. • RTL design of the Datapath blocks, such as the Interleaver, Scrambler and Frame Aligner. • Mixed-Mode simulation and verification of the Phase-Shifter block using SystemVerilog. • Design and Simulation of the on-chip Temperature Sensor (IC Design, from schematic to layout) Show less

Undergraduate Teaching Assistant

• Sep 2012 - Jun 2016

Teaching assistant for Calculus, Physics, Circuit Theory, and the laboratory classes of Electronics and C programming Teaching assistant for Calculus, Physics, Circuit Theory, and the laboratory classes of Electronics and C programming

Graduate Research Intern

• Jul 2015 - Sep 2015

Collaboration in the design, implementation and synthesis of the digital calibration block of a Reconfigurable Millimeter-Wave All-Digital PLL. Collaboration in the design, implementation and synthesis of the digital calibration block of a Reconfigurable Millimeter-Wave All-Digital PLL.