Experience

Dolphin Design

• France
• Semiconductor Manufacturing
• 100 - 200 Employee

• IP architect and Lead Digital Design Engineer

  • Jan 2019 - Present

  IP architect for the new core-agnostic low-power multi-core MCU platform from Dolphin Design:- main contributor to product roadmap (market analysis, features definition)- responsible of product documentation (datasheet, user manual)- interaction with clients (support) and prospects (technical meetings)- strong interaction with SW team (to help support of CMSIS-Driver)- strong interaction with our ASIC team (to help characterize our product using ULPmark benchmark)Also in charge of several design&verification tasks:- ARM Mx core and Coresight debug system integration (in single- and multi-core configurations)- several RISCV-compatible cores integration (from OpenHW, lowRISC, ...)- RISCV-compatible debug system integration- clock-gating improvements- several RTL modules (HW semaphores, clock&reset)- improvements of our SystemVerilog/UVM testbench- added support of the UVM register model- added support of ARM and RISCV GCC toolchains in our testbench (Makefiles, LD scripts, ...) Show less

• Digital Verification Engineer

  • Jun 2018 - Jan 2019



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• TOP integrator - aborted

  • Aug 2016 - Sep 2016

  We were requested by ST to start integrating various IPs (USB, PCIe, GEth, Cortex A9 ...) but the project was finally taken back by the originating ST team. We were requested by ST to start integrating various IPs (USB, PCIe, GEth, Cortex A9 ...) but the project was finally taken back by the originating ST team.



Teledyne e2v

• United Kingdom
• Appliances, Electrical, and Electronics Manufacturing
• 700 & Above Employee

• RTL design engineer

  • Oct 2015 - Jun 2016

  I was responsible for the RTL design of most of the digital blocks of a new high performance 16Mpix image sensor. o Design of 90% of image processing blocks:
  - digital gain, HDR correction, black correction, default correction, FIFO management, statistics, context insertion o Design of two image matrix control blocks: -
  ADC and pixel shifters controls I also participate in: o blocks synthesis o register bank generation o TOP verification o TOP verification environment improvement:
  - PERL scripted automatic register tests generation
  - Simplification and mutualization of environment TCL scripts o Taking an active part in the architecture definition (for the algorithms block) Show less



PYXALIS

• France
• Semiconductor Manufacturing
• 1 - 100 Employee

• RTL design engineer

  • Nov 2013 - Sep 2014

  I was responsible for the RTL design of several critical blocks of a new high performance image sensor based on the Cortus 32bit APS3 processor. Amongst them were: o The complete inter-blocks asynchronous bus(master, slaves and XBAR) with Cortus APS3 compatible interfaces o 8bit SPI slave IF for Cortus APS3 o High Dynamic Range(HDR) Black Levels correction algorithms block(main IP in this SoC) I also participate in: o register bank generation o verification of a serializer block used on the CMOS/LVDS pads o Taking an active part in the architecture definition (for the algorithms block) Show less



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• TOP RTL integrator engineer

  • Sep 2012 - Feb 2013

  I worked on the STEricsson power management processor A8680 taking part in the following tasks: o TOP RTL integration o Updates on testbenches to meet verification team new requirements o Beta test of register generation new methodology and scripting o Took an active part in architecture definition I worked on the STEricsson power management processor A8680 taking part in the following tasks: o TOP RTL integration o Updates on testbenches to meet verification team new requirements o Beta test of register generation new methodology and scripting o Took an active part in architecture definition



EASii IC

• Semiconductor Manufacturing
• 1 - 100 Employee

• TOP integrator lead

  • Jun 2012 - Sep 2012

  We were requested by ST Edinburgh to update an existing image sensor with some changes in architecture. As specifications changed during project’s course I took more responsibilities been directly involved with client through direct contact, meetings and travel to client’s site. My main activities in this project were: o RTL team leader and top RTL integrator o Integration support for the DFT, FW and backend teams o Participation to inter teams meetings and architecture decisions with client Show less



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• Design/TOP integrator engineer (freelance)

  • 2010 - 2011

  Working on the STEricsson application processor Nova A9540 I expanded my abilities and my knowledge of the frontend flow by taking part in the following tasks: o TOP RTL integration o BIST insertion using Spyglass o Integration support for the DFT team o ECO and formal proof o Design support for some IPs mainly of the hardware video decoder Working on the STEricsson application processor Nova A9540 I expanded my abilities and my knowledge of the frontend flow by taking part in the following tasks: o TOP RTL integration o BIST insertion using Spyglass o Integration support for the DFT team o ECO and formal proof o Design support for some IPs mainly of the hardware video decoder



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Design engineer

  • 2009 - 2010

  I pursued with the same team as before but for the then newly created STEricsson on the NovaThor platform. My main tasks consisted of: o CtoRTL design and synthesis : DMA HW controller o Support and update of previous designs on U8500 platform I pursued with the same team as before but for the then newly created STEricsson on the NovaThor platform. My main tasks consisted of: o CtoRTL design and synthesis : DMA HW controller o Support and update of previous designs on U8500 platform



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• Design engineer

  • 2007 - 2009

  As a way to improve the performances of the hardware video decoder, it was decided to use a High Level Synthesis CtoRTL methodology. I was mainly involved in bringing this new methodology to fit the requirements of control-oriented designs as needed by IPs handled in the video team.My main tasks consisted of:o CtoRTL flow early user giving feedback and serving as interface between design architect and EDA tool vendor Synfora Inc.o CtoRTL redesign and synthesis : Motion estimator Cache memory for motion estimationo Specification and RTL design of a video bitstream decoder supporting MPEG4, H264, VC1 and JPEG Show less

• Design/Verification engineer

  • 2006 - 2007

  o RTL design of a cache memory for video motion estimation (MPEG4, H264) on smartphone platform U8500.o Verification at top level of the video hardware accelerator for MPEG4 codec.



EPFL (École polytechnique fédérale de Lausanne)

• Switzerland
• Higher Education
• 700 & Above Employee

• Research assistant

  • Oct 2005 - Jan 2006

  Theoretical study of Doppler effect filtering algorithms for mobile digital TV terminals in collaboration with ABILIS Systems, Geneva Theoretical study of Doppler effect filtering algorithms for mobile digital TV terminals in collaboration with ABILIS Systems, Geneva



LIRMM

• France
• Research Services
• 1 - 100 Employee

• Internship

  • Feb 2005 - Jul 2005

  I was in charge of specifying and designing a reconfigurable cryptographic coprocessor for symmetric algorithms (DES, AES, RC4, etc.) using the 32bit low-cost APS3 processor from CORTUS, Montpellier. www.cortus.com/cryptographic_coprocessor.pdf I was in charge of specifying and designing a reconfigurable cryptographic coprocessor for symmetric algorithms (DES, AES, RC4, etc.) using the 32bit low-cost APS3 processor from CORTUS, Montpellier. www.cortus.com/cryptographic_coprocessor.pdf