John McKeown

ASIC Verification Engineer at Schrader Electronics
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Contact Information
us****@****om
(386) 825-5501
Location
Belfast Metropolitan Area, UK

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Experience

    • United Kingdom
    • Automotive
    • 100 - 200 Employee
    • ASIC Verification Engineer
      • May 2015 - Present

  • Entropic Communications
    • Belfast, United Kingdom
    • Senior Design Engineer
      • 2012 - Feb 2015

      Authority on firmware test and verification for production video firmware releases. Responsible for build and release for a number of SDK branches. Triage and debug of SQA and customer video firmware issues. Responsible for SoC validation testing. Maintenance and enhancement of a software driver application, including a firmware API interface, used to control a HAPS FPGA SoC test system. Development of HAPS FPGA test systems for Video Codec IP prototyping and test. Responsible for FPGA validation of Video Codec IPs, including HEVC, H264, MP2, MP4. Show less

    • United States
    • Semiconductor Manufacturing
    • 100 - 200 Employee
    • Senior Design Engineer
      • 2010 - 2012

      Same description as for Entropic Communications above. Same description as for Entropic Communications above.

    • Netherlands
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Senior Design Engineer
      • 2008 - 2010

      Same description as for Entropic Communications above. Same description as for Entropic Communications above.

    • United States
    • Semiconductors
    • 300 - 400 Employee
    • Design Engineer
      • 2006 - 2008

      Same description as for Entropic Communications above. Same description as for Entropic Communications above.

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Senior Product Performance Engineer
      • 1997 - 2006

      Responsible for final software speed file delivery. Initial silicon debug work and design troubleshooting. Introduced Minimum Cycle Time and BIST performance testing methodology for Spartan3 FPGA family. Product/Test Engineer for High Volume FPGA devices. Development of test HW and SW for Credence SC212 and Teradyne J750 test systems. RMA (Customer returns) lab failure analysis work. Responsible for final software speed file delivery. Initial silicon debug work and design troubleshooting. Introduced Minimum Cycle Time and BIST performance testing methodology for Spartan3 FPGA family. Product/Test Engineer for High Volume FPGA devices. Development of test HW and SW for Credence SC212 and Teradyne J750 test systems. RMA (Customer returns) lab failure analysis work.

Education

  • Queen's University Belfast
    Electrical and Electronics Engineering, BEng 2.1 Hons

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