Sr Verification Engineer

• Sep 2020 - Present

Perform functional verification on power management products. - Block-level and top-level verification - Constrained random testbenches - SystemVerilog assertions - Coverage analysis Perform functional verification on power management products. - Block-level and top-level verification - Constrained random testbenches - SystemVerilog assertions - Coverage analysis

Verification Engineer, Senior Staff

• Feb 2018 - Dec 2019

Perform functional verification on motion sensor products for smartphones. Perform functional verification on motion sensor products for smartphones.

Design Verification Engineer

• Oct 2015 - Dec 2017

Performed functional verification on mixed-signal touch screen controller products. Performed functional verification on mixed-signal touch screen controller products.

Functional Verification Consultant

• 2011 - 2014

Performed functional verification on several touch screen controller projects. Made extensive use of real value modeling using Verilog-AMS, SystemVerilog, assertions, and constrained random testbenches. Implemented custom SystemVerilog and Verilog-AMS schematic netlisters to support full-chip mixed signal simulation using a digital simulator. Performed functional verification on several touch screen controller projects. Made extensive use of real value modeling using Verilog-AMS, SystemVerilog, assertions, and constrained random testbenches. Implemented custom SystemVerilog and Verilog-AMS schematic netlisters to support full-chip mixed signal simulation using a digital simulator.

Principle Member of Technical Staff

• 2000 - 2010

.Functional Verification – Verification planning, testbench implementation, design debug, coverage analysis, regression flows, data management. • Microcontrollers, CODECs, SAS expanders, and telecom products. • Implemented digital and mixed-signal simulation methodologies. • Promoted use of SystemVerilog within the company. Prepared training material, conducted training sessions, and provided tool support. Software Development - Developed and supported a platform design system for a TTA-based microcontroller. This included developing a proprietary design language and writing its corresponding parser. This became the standard design methodology for implementing MaxQ-based System-on-Chip products. Show less

Adjunct Lecturer - Electrical Engineering

• 2000 - 2003

Created and taught graduate courses in Design Automation and Functional Verification during three summer semesters. Created and taught graduate courses in Design Automation and Functional Verification during three summer semesters.

Senior Engineer

• 1998 - 1999

Primary resource for Cadence dfII tool support and verilog netlister flow enhancements. • Coded an Ikos netlister in SKILL. • Implemented an Hspice netlist scaling utility in Perl. • Wrote a cross‐view checker to ensure consistency across various representations of a cell. • Implemented a cell boundary checker using SKILL and Hercules. Primary resource for Cadence dfII tool support and verilog netlister flow enhancements. • Coded an Ikos netlister in SKILL. • Implemented an Hspice netlist scaling utility in Perl. • Wrote a cross‐view checker to ensure consistency across various representations of a cell. • Implemented a cell boundary checker using SKILL and Hercules.

Software Design Engineer

• Jan 1996 - 1998

Provided EDA tool support to a global design community. Implemented customizations to the Cadence dfII design environment. Focused primarily on backend tools and flows including the layout editor, automatic place and route, and LVS. Provided EDA tool support to a global design community. Implemented customizations to the Cadence dfII design environment. Focused primarily on backend tools and flows including the layout editor, automatic place and route, and LVS.

Programmer

• 1990 - 1991

Electronic Technician

• 1980 - 1982