Joao Puga
Operations Manager at G9Telecom, S.A.- Claim this Profile
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Bio
Experience
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G9Telecom, S.A.
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Portugal
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Telecommunications
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1 - 100 Employee
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Operations Manager
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Jun 2019 - Present
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Altice Labs
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Telecommunications
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700 & Above Employee
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Hardware Engineer / FPGA Developer
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Sep 2008 - Present
Main activities and responsibilities: FPGA design for telecommunication equipments: specification, implementation, simulation, test, hardware debug and prototypes validation; Technical Team Leader; FPGA’s architecture definition based on telecommunication normative documents; Working closely with hardware, software and quality assurance engineers during tests and integration. Technical skills and competences: Solid experience in RTL coding (VHDL) and creating schematic diagrams using Mentor Graphics HDL Designer Experience with the following EDA tools: ModelSim, Altera Quartus, Xilinx ISE, Synplify PRO. Experience with Xilinx Spartan3, Virtex5 and Altera ArriaII, ArriaV, StratixIV, StratixV, Arria 10, Stratix 10 devices. Experience in running STA analysis and achieving timing closure. Experience using high speed transceivers, DDR2/3 memory interfaces and standard design structures applied to packet processing (FIFO’s, memories, state machines,…) Experience with laboratory test equipment tools (oscilloscope, Ixia traffic generator, SignalTap/Chipscope). In-depth knowledge of several network protocols, such as: Ethernet, MPLS, L2CP, MII/GMII/RGMII, XAUI, HIGIG; GPON/XGPON/NGPON2 technology; OAM mechanisms Show less
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Synopsys Inc
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United States
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Software Development
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700 & Above Employee
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Project Engineering Manager
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Jan 2018 - May 2019
- Understand and assist in the generation of design specifications. - Participate and manage Mixed-Signal IP Projects. - Create and maintain Project Planning. - Work toward improving efficiency in design procedures and methodologies - Understand and assist in the generation of design specifications. - Participate and manage Mixed-Signal IP Projects. - Create and maintain Project Planning. - Work toward improving efficiency in design procedures and methodologies
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Education
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Universidade de Aveiro / University of Aveiro
Master in Electronics and Telecommunications Engineering, 16/20