Joan Whelan

Outgoing Quality Control Engineer & Supervisor at JIREH SEMICONDUCTOR INCORPORATED
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Contact Information
us****@****om
(386) 825-5501
Location
Portland, Oregon Metropolitan Area

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Experience

    • United States
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Outgoing Quality Control Engineer & Supervisor
      • Jul 2017 - Mar 2019

      Portland, Oregon Area - Driving changes to both the inline and outgoing inspection by creating inspection procedures and specifications, creating a library of defect images, and utilization of internal web-based reporting to quickly inform the organization of critical defects which need attention. These changes are leading to a more rapid response and resolution by process engineers, and a reduction in scrap material. - Managing a group of 9 technicians and 1 supervisor. Management includes training, evaluating… Show more - Driving changes to both the inline and outgoing inspection by creating inspection procedures and specifications, creating a library of defect images, and utilization of internal web-based reporting to quickly inform the organization of critical defects which need attention. These changes are leading to a more rapid response and resolution by process engineers, and a reduction in scrap material. - Managing a group of 9 technicians and 1 supervisor. Management includes training, evaluating and developing staff to enable career development and continuous improvement. - Enhanced communication and collaboration with overseas Incoming Quality Control group. Show less

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Real-time Defect Analysis Engineer
      • Jun 2015 - Aug 2016

      Boise, Idaho Area - Identified in-line defects on 3D Cross-point memory wafers and worked with process engineering to resolve issues. Liaison with out-of-state manufacturing site for technology transfer. Responsibilities included updates at daily tactical meetings, commons studies to correlate process tools/recipes with defects, correlation of defects with probe data and formal reports.

    • Higher Education
    • 700 & Above Employee
    • Professional training at Oregon State University, Electron Microscopy Lab.
      • Feb 2015 - May 2015

      Corvallis, OR Updated analysis skills on a FEI Quanta 3D Dual Beam SEM/FIB.

    • Printing Services
    • 100 - 200 Employee
    • Principal Failure Analysis Engineer
      • Jul 2010 - Sep 2014

      Sydney, Australia - Led Failure Analysis (FA) investigations of customer returns and next generation inkjet printheads. Greatly improved worldwide corporate satisfaction with FA group by reinventing and optimizing interactions with customers, engineers and management, and working across organizations to determine root cause of failures. Results enabled customers and internal partners to significantly improve yields and product performance. - Developed and documented FA procedures and best practices. Trained… Show more - Led Failure Analysis (FA) investigations of customer returns and next generation inkjet printheads. Greatly improved worldwide corporate satisfaction with FA group by reinventing and optimizing interactions with customers, engineers and management, and working across organizations to determine root cause of failures. Results enabled customers and internal partners to significantly improve yields and product performance. - Developed and documented FA procedures and best practices. Trained FA technicians and engineers. - Liaisoned with universities and analytical laboratories for surface analyses and materials characterization. Show less

    • United States
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Failure Analysis Engineer
      • Sep 1999 - Dec 2008

      Corvallis, OR - FA lead in solving problems of both thermal and piezoelectric inkjet print heads, wafer fab line downs and yield loss issues. Findings enabled product engineers to quickly solve problems and improve processes. - Developed characterization strategies, facilitated and directed analyses, and communicated the results of analyses performed in an internal analytical lab which had the following tool sets: SEM/EDS, TEM, XRD, XPS, Auger, TOF SIMS, AFM, FTIR, GC/MS, LC/MS, ICP, DSC, X-ray… Show more - FA lead in solving problems of both thermal and piezoelectric inkjet print heads, wafer fab line downs and yield loss issues. Findings enabled product engineers to quickly solve problems and improve processes. - Developed characterization strategies, facilitated and directed analyses, and communicated the results of analyses performed in an internal analytical lab which had the following tool sets: SEM/EDS, TEM, XRD, XPS, Auger, TOF SIMS, AFM, FTIR, GC/MS, LC/MS, ICP, DSC, X-ray tomography, optical microscopy. - Collaborated with operations staff and equipment maintenance team to improve wafer yield analysis cycle time, quality of yield reports, process documentation and SEM equipment uptime. - Worked with a cross-functional team from several HP sites and outsource vendors on an R&D memory device. Determined cause of failures for electron emitters, memory media and Si MEMS micromovers. Investigated 3D x-ray tomography for metrology of emitters.

    • Manufacturing Development Engineer
      • May 1996 - Sep 1999

      Corvallis, OR - Developed wet etch procedures for silicon substrates to enable better product performance and yields. Utilized Design of Experiments (DOE) to optimize process, and SPC for continuous process monitoring and improvement. Trained technicians and, later, Singapore engineers for transfer of process to Singapore site. Collaborated with R&D team to develop FMEA for Si etch-related project prioritization. - Organized and led Worldwide Metrology Core Team consisting of managers and engineers to… Show more - Developed wet etch procedures for silicon substrates to enable better product performance and yields. Utilized Design of Experiments (DOE) to optimize process, and SPC for continuous process monitoring and improvement. Trained technicians and, later, Singapore engineers for transfer of process to Singapore site. Collaborated with R&D team to develop FMEA for Si etch-related project prioritization. - Organized and led Worldwide Metrology Core Team consisting of managers and engineers to develop project plans for the creation, certification, maintenance and documentation of calibration standards for cases where NIST standards were unavailable. - Brought up an optical linewidth measurement system for critical dimension metrology and subsequently developed procedures for worldwide cross calibrations of linewidth measurements for both internal sites and outsource vendors, enabling agreement on measurements and eliminating product loss due to out-of-spec features. Performed Gauge R&R studies and SPC.

    • United States
    • Semiconductors
    • 700 & Above Employee
    • Senior Process Engineer
      • Oct 1994 - Apr 1996

      Lowell, MA - Responsible for photolithography and dry etch processes in GaAs wafer Fab; directed team of eight engineering assistants. Documented Fab processes for ISO9001 audit. Utilized SEM analyses for process development and troubleshooting. - Brought up a GCA i-line stepper to replace the contact aligners, leading to a 30% improvement in visual defect yield. - Brought up a Matrix Downstream Plasma Etcher for SiN, which increased the dry etch capacity through the Fab.

    • Materials Characterization & Quality Assurance Engineer
      • Aug 1991 - Jun 1994

      Broomfield, CO - Developed testing and calibration procedures for determination of carrier concentration and Hall mobility in GaAs, AlGaAs and InGaAs epitaxial layers (for MESFETs, HEMTs and HBTs). Directed team of four technicians. - Communicated with, and prepared reports for: external customers, materials growth engineers, managers and VP regarding characterization results. - Implemented SPC of testing procedures, enabling quick identification of special causes of variation, thereby generating… Show more - Developed testing and calibration procedures for determination of carrier concentration and Hall mobility in GaAs, AlGaAs and InGaAs epitaxial layers (for MESFETs, HEMTs and HBTs). Directed team of four technicians. - Communicated with, and prepared reports for: external customers, materials growth engineers, managers and VP regarding characterization results. - Implemented SPC of testing procedures, enabling quick identification of special causes of variation, thereby generating consistent and reliable results. Show less

Education

  • University of California, Berkeley
    Master of Science (MS), Materials Science and Engineering
  • Sonoma State University
    Bachelor of Science (BS), Chemistry

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