Experience

成都海光

• China
• Environmental Services

• Member Of Technical Staff

  • Apr 2018 - Present

  Work in Verification Division of SoC Design Center, responsible for the PCIE like PCS verification in DXIO, which plays the role of the Die_to_Die and Socket_to_Socket communication Lead the Unified Regression System implementation over all SoC divisions to unify the regression flow Lead the GOP_PCS, GMI_PCS and WAFL_PCS verification in IP level and DXIO subsystem level Lead the GOP_PCS, GMI_PCS and WAFL_PCS re-usable verification environment development Lead the GOP_PCS, GMI_PCS and WAFL_PCS testbench reuse structure development between IP level and DXIO subsystem level Patent: A chip verification method, device, chip and storage media [App Num: 202010540313.1] Patent: Regression management methods, storage media management methods, devices and media [App Num: 202011414318.6] Patent: Regression methods, system, devices and readable storage media [App Num: 202011358331.4] Patent: Methods, devices for the ignore bins auto-generation of the crossing cover points [App Num: 202011556329.8] Patent: Chip verification methods, devices, storage media [App Num: 202011495163.3] Show less



AMD

• France
• Architecture and Planning
• 1 - 100 Employee

• Member Of Technical Staff

  • Jun 2017 - Apr 2018

  Work in GFX (Graphics) DFP (Design for Power) Division, and responsible for the harvesting related power management verification of GFX system IP Harvesting configuration plan and management with global design team Functional coherence verification of each block IP in GFX with various harvesting configurations Verification of the working status, drawing and computing traffic distribution and performance impact of harvested blocks Work in GFX (Graphics) DFP (Design for Power) Division, and responsible for the harvesting related power management verification of GFX system IP Harvesting configuration plan and management with global design team Functional coherence verification of each block IP in GFX with various harvesting configurations Verification of the working status, drawing and computing traffic distribution and performance impact of harvested blocks



LSI, an Avago Technologies Company

• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Verification Engineer

  • Jul 2012 - Jun 2017

  Worked with SEQ design/verification global team of Data Controller DivisionRich knowledge of UVM methodology based verificationFactory based override for codes reuse with different configurationsUVM components development and communication via TLM ports, including Test, Environment, Sequencer/Driver and Monitor/ScoreboardSequence scheduling for complex test scenariosScenario/Behavior level configuration for simplifying tests developmentRich experience of verification flowTest Plan review based on feature SPECTestbench development of scenario creation, interface communication, functional modeling, etc.FCOV tracking for scenarios/configurations completenessRegression passing rate tracking for RTL quality and bug closureCCOV holes analysisVerification review for verification completeness Mainly focus on the functional features as Parity Sector Soft Decoding, Signal Alignment, Retry combination, etc. Show less

• Verification Engineer

  • Jul 2012 - Nov 2015

  Worked with SEQ design/verification global team of Data Controller DivisionGood knowledge of OVM methodologyDirected/Random tests development based on OVM phase and randomization constraintDUT drivers development using virtual interfaceMonitor/Scoreboard development for functional modeling and comparisonProperty based assertion for protocal/timing checkerFCOV development based on covergroup and cover propertyTests regression debug using VCS, Verdi, Vplan, etc.Mainly focus on the functional features as SyncMark detection, Signal Alignment, R2DE, etc. Show less



英伟达

• China
• IT Services and IT Consulting

• Intern

  • Jul 2011 - Nov 2011

  Worked in Video ASIC Design Division Regression results extraction and analysis based on Perl script Gated clock RTL desgin Worked in Video ASIC Design Division Regression results extraction and analysis based on Perl script Gated clock RTL desgin