Experience

Marvell Semiconductor

• 1 - 100 Employee

• Senior Design Engineer & Manager

  • May 2014 - Present

   Developed Marvell new DSP processor, including: Understanding the architecture and doing feasibility check, Coding the IFU IF1~IF3 and EXUNIT EX1~EX4 RTL and writing assertions and monitors for IFU, debugging the assembly code tests, and fixing timing and improving performance. Besides, I also integrated an L2 Cache into this new DSP processor. The final product is a 14-stage, 1GHz, high performance DSP core for communication baseband SOC. Led a RTL team with 5 team members. My team focused on RTL development for ARM v8 and Marvell DSP processor. Show less

• Senior Design Engineer

  • May 2011 - Apr 2014

   Worked on a Marvell in-house processor based on ARM v8 architecture. I developed RTL for ALU, flag, bypass unit and IDU’s ARM v8 (excluding Neon) part. I also wrote assertion，monitor for these units. Besides that, I worked on verification for floating-point adder and multiplier, and achieved 100% coverage for the two units. I also worked on the performance optimization for the core.



AMD

• France
• Architecture and Planning
• 1 - 100 Employee

• CAD engineer

  • Aug 2010 - Apr 2011

   Master AMD GPU Front End Synthesis Flow: PTF and Supra  Support first Power Gating GPU Chip, master UPF/CPF low power synthesis, formal verifation, and MVRC  Write check script for UPF/CPF flow, about 5000-line perl script  Test flow issue for Design Compiler and Formality, a lot of debug experience  Master AMD GPU Front End Synthesis Flow: PTF and Supra  Support first Power Gating GPU Chip, master UPF/CPF low power synthesis, formal verifation, and MVRC  Write check script for UPF/CPF flow, about 5000-line perl script  Test flow issue for Design Compiler and Formality, a lot of debug experience