Experience

Rivos Inc.

• United States
• Computer Hardware Manufacturing
• 100 - 200 Employee

• CPU RTL Architect

  • Oct 2021 - Present



Apple

• United States
• Computers and Electronics Manufacturing
• 700 & Above Employee

• CPU Architect

  • Apr 2013 - Oct 2021



Arm

• United Kingdom
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Principal Design Engineer

  • Dec 2006 - Apr 2013

  Member of ARM ARB (Architecture Review Board) Cortex A57 (Atlas) ARMv8 processor - Core microarchitect - Design of dispatch and completion unit Cortex A15 (Eagle) ARMv7 processor - Contributed to microarchitecture development - Designed dispatch and completion unit - Contributed to other units: designed rename, predicted target queue, and reservation stations Cortex A9 (Falcon) - Redesigned NEON control logic for higher frequency and out-of-order pipeline interface Show less



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Engineer

  • Oct 2003 - Dec 2006

  Cortex A8 (Tiger/Ferrari) - Implemented instruction decode and issue unit - Designed and implemented physical methodology and flow Cortex A8 (Tiger/Ferrari) - Implemented instruction decode and issue unit - Designed and implemented physical methodology and flow



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Component Engineer

  • Jun 2002 - Aug 2003

  Pentium 4 (Tejas) - Implemented memory subsystem datapath blocks Pentium 4 (Tejas) - Implemented memory subsystem datapath blocks



Centaur Technology

• United States
• Computer Hardware Manufacturing
• 1 - 100 Employee

• Senior Engineer

  • Apr 1999 - Jun 2002

  C5X/C5XL/C5Z - Designed x87 control logic: decode, dispatch, execute pipeline control, ROB (reorder buffer), and completion C5B/C5C/C5X/C5XL/C5Y/C5Z - Designed L2 cache memory system C5A - Designed MTRR and misc control logic for L1 cache memory system C5X/C5XL/C5Z - Designed x87 control logic: decode, dispatch, execute pipeline control, ROB (reorder buffer), and completion C5B/C5C/C5X/C5XL/C5Y/C5Z - Designed L2 cache memory system C5A - Designed MTRR and misc control logic for L1 cache memory system



Motorola Mobility (a Lenovo Company)

• United States
• Computers and Electronics Manufacturing
• 700 & Above Employee

• Design Engineer

  • Nov 1992 - Apr 1999

  PPC 7450 (V'ger) - Contributed to memory system microarchitecture development - Designed L3 cache memory system - Worked with other companies on specification of next generation source synchronous, high speed SRAM (Habanero) - Designed load side bus interface (6XX) MCF5202/5203 - Designed L1 unified cache memory system MC68040 (LP040/HP040) - Redesigned L1 data cache memory controller for static operation and synthesis flow PPC 7450 (V'ger) - Contributed to memory system microarchitecture development - Designed L3 cache memory system - Worked with other companies on specification of next generation source synchronous, high speed SRAM (Habanero) - Designed load side bus interface (6XX) MCF5202/5203 - Designed L1 unified cache memory system MC68040 (LP040/HP040) - Redesigned L1 data cache memory controller for static operation and synthesis flow



Intergraph

• United States
• Software Development
• 700 & Above Employee

• Design Engineer

  • Apr 1990 - Nov 1992

  SBGA - Designed various sections: SBus master interface, SBus slave interface, and interrupt controller FDDI - Redesigned FDDI board for enhanced SRX bus performance SBGA - Designed various sections: SBus master interface, SBus slave interface, and interrupt controller FDDI - Redesigned FDDI board for enhanced SRX bus performance