Experience

NeuroPace

• United States
• Medical Equipment Manufacturing
• 100 - 200 Employee

• Principal Design Engineer

  • May 2019 - Present

  Low noise low power sensing front end design, sigma delta ADC, digital low and high pass filter design. SOC chip architect. Implantable medical devices design and verification. Low noise low power sensing front end design, sigma delta ADC, digital low and high pass filter design. SOC chip architect. Implantable medical devices design and verification.



Western Digital

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Principal analog IC design engineer

  • Jul 2016 - Apr 2019

  Non Volatile memory SOC design (ReRAM and PCM). Block-level and full-chip block design and verification. Focus on Analog circuitry such as oscillators and regulators. Non Volatile memory SOC design (ReRAM and PCM). Block-level and full-chip block design and verification. Focus on Analog circuitry such as oscillators and regulators.



SanDisk

• Senior Analog IC Designer

  • Feb 2013 - Jun 2016

  Chip-level circuits design/verification of 3D ReRAM, 2D NAND flash memory. Chip-level circuits design/verification of 3D ReRAM, 2D NAND flash memory.



Aptina

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Sr. Analog IC designer

  • Oct 2011 - Jan 2013

  Design voltage boosters, SAR ramp ADC for CMOS image sensors in cell phone and camera applications. Design voltage boosters, SAR ramp ADC for CMOS image sensors in cell phone and camera applications.



St. Jude Medical

• United States
• Medical Equipment Manufacturing
• 700 & Above Employee

• Analog IC Designer

  • Jan 2009 - Jul 2011

  • Design/Debug following critical circuits for biomedical implant telemetry applications: sigma-delta ADC, telemetry transmitter and receiver, 1MHz 2nd order PLL. • Design low-leakage and low-power digital circuit at the system level: telemetry communication protocol. • Complete product release cycle from schematic, layout, testing, and reliability. Design ESD network and generate test plan and documents for ATE. • Design/Debug following critical circuits for biomedical implant telemetry applications: sigma-delta ADC, telemetry transmitter and receiver, 1MHz 2nd order PLL. • Design low-leakage and low-power digital circuit at the system level: telemetry communication protocol. • Complete product release cycle from schematic, layout, testing, and reliability. Design ESD network and generate test plan and documents for ATE.



Information Sciences Institute

• United States
• Research
• 200 - 300 Employee

• Research assistant

  • Aug 2002 - Dec 2008

  • Develop the world's first hippocampus neuron modeling IC verified in vitro. • Design an adaptive, 20uW band-pass biomedical amplifier. • Develop the world's first hippocampus neuron modeling IC verified in vitro. • Design an adaptive, 20uW band-pass biomedical amplifier.



IBM Global Services

• India
• Consumer Services
• 1 - 100 Employee

• IT specialist

  • Oct 1998 - Jul 2001

  • Lead a team of seven engineering service representatives nationwide. • Sign service contracts with $1M annual revenue. • Lead a team of seven engineering service representatives nationwide. • Sign service contracts with $1M annual revenue.