Experience

Rivos Inc.

• United States
• Computer Hardware Manufacturing
• 100 - 200 Employee

• Principal Member of Technical Staff - Power Management Architecture

  • Jul 2022 - Present



Huawei

• China
• Telecommunications
• 700 & Above Employee

• Principal Researcher

  • Aug 2021 - Jul 2022



ETH Zürich

• Switzerland
• Higher Education
• 700 & Above Employee

• Senior Researcher

  • Aug 2019 - Aug 2021



Institute of Microelectronics

• Singapore
• Research Services
• 100 - 200 Employee

• Scientist III

  • Jul 2018 - Jul 2019

  Deep Learning scientist working on a multi-year program that aims to build next generation hardware for deep learning beyond GPUs and TPUs, the program introduces optimizations in the whole stack from DL algorithm down to fabrication. Deep Learning scientist working on a multi-year program that aims to build next generation hardware for deep learning beyond GPUs and TPUs, the program introduces optimizations in the whole stack from DL algorithm down to fabrication.



Nanyang Technological University Singapore

• Singapore
• Higher Education
• 700 & Above Employee

• Research Scientist

  • Apr 2017 - Jul 2018

  Leading the Architecture and the Design of a state of the art lightweight secure processor, with industry collaboration. The processor is based on the modern architecture of ISA RISC-V with the following key features: • Secure Boot • Trusted Execution Environment (TEE) based co-processor • Memory Encryption and Integrity • Secure Debug and IOs • Key Generation and Management • Remote Attestation Leading the Architecture and the Design of a state of the art lightweight secure processor, with industry collaboration. The processor is based on the modern architecture of ISA RISC-V with the following key features: • Secure Boot • Trusted Execution Environment (TEE) based co-processor • Memory Encryption and Integrity • Secure Debug and IOs • Key Generation and Management • Remote Attestation



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• System and SoC Architect

  • Jul 2014 - Feb 2017

  • Working on the definition of the SOC interconnect requirements and specification of Intel client SOC • Working on the integration of USB TypeC sub-system into Intel client SOC including system level requirements and flows.• Working on integration of new IPs into the SOC• Defining new Power-Management flows and features to meet the power, performance and bandwidth requirements of the SOC interconnect

• Power Management Architect

  • Jan 2010 - Jul 2014

  Power management architect for the next generation ultrabook Intel processors.Working on innovating and defining new features, algorithms, flows, power delivery solutions, chipset and platform components management in order to meet all day battery life for next generation ultrabook Intel processors. - Architectural definition of the CPU, Chipset and Platform power management features - High Level Architectural Specification owner of CPU C-states & S-states - Inter and Intra department Collaboration with design, validation chipset and platform teams - Developing, improving and innovating features for low powerThe work includes: reviewing competitive SOCs power data and build strategy for better power targets, cross site (Israel, USA, and India) work, collaboration and many business trips to work and sync with the several teams, work with OS and driver teams, system level (CPU/GPU/Memory/IOs/Display/Imaging/...) power feature to reduce overall energy at interesting mobile scenarios (Video playback, Video conferencing, Video capturing, connected-standby, ...) Show less

• Power Management Validation Engineer

  • Jan 2005 - Jan 2010

  Power Management Validation Engineer, worked on validating CPU power management features, in additional to interaction with platform and chipset.gained knowledge on architecture and micro-architecture of Intel CPU and chipsetworked with various validation and design tools to make sure that the power management features are implemented correctly according to the specification During my work as Validation Engineer I have gained the required tools, knowledge, qualification and high level view that contributed much to my success as architect Show less

• Power Management Validation Student

  • Jan 2004 - Jan 2005

  I was student for Msc in computer science when started to work at Intel at the Power Management Validation team.Learned Intel architecture micro-architecture and validation technologies. Worked on the validation of CPU Power Management features