Jason Glass
Member of Research Staff at HYPRES, Inc- Claim this Profile
Click to upgrade to our gold package
for the full feature experience.
Topline Score
Bio
Experience
-
HYPRES, Inc
-
United States
-
Research
-
1 - 100 Employee
-
Member of Research Staff
-
May 2022 - Present
• Provided Expertise in the FPGA and general computer hardware realms to a team of cryogenic engineers, extending the capabilities of the team to further augment our capability of making new products • Adapted Xilinx documentation and references to a variety of customer-driven designs that employed a large selection of available Xilinx FPGA peripherals (Ex: Ethernet, JTAG, UART, GTY/GTX Transceivers, Flash, DDR4) • Expanded upon existing projects driving state-of-the-art ADCs and performing FFTs on over 120 Gigabits per seconds (Gbps) of data • Bridged gap between Superconducting design engineers and customers to program FPGAs that delivered objective level of performance • Drove development of a RTOS that interfaced with standard lab equipment like high-performance Agilent, HP and MPC Signal Generators, networked Power switches, SRS Temperature Controllers, custom designed Current Generators, and Cryogenic Hardware such as compressors, Pressure Gauges and helium pumps. Show less
-
-
-
Optimum Semiconductor Technologies Inc.
-
Wireless Services
-
1 - 100 Employee
-
Member Of Technical Staff
-
Nov 2018 - May 2022
• Designed PCIe software interface to a neural-network FPGA architecture, and implemented memory optimizations to meet design goals • Conducted verification of RTL derived from C models and Python models, using Modelsim and VCS, as well as FPGA hardware verification • Developed knowledge of ASIC and FPGA timing and design requirements, learned key differences between the two • Gained Expertise in the use of Xilinx Vivado Design Suite, the design of Xilinx specific constraints, and debugging functional simulation mismatches between behavioral, post-synthesis and post-implementation netlists • Augmented bitstream testing protocols. Pioneered proactive reusable and automated testing features that aided in the precision and accuracy of regression test • Performed testing, experimentation, and integration of black-box DSP, BRAM, DDR4, GDDR6 and AXI IP from outsider vendors, such as Achronix, Xilinx and Intel • Worked autonomously to develop high-level Bash, Python and TCL scripts to automate various stages of RTL design and test cycle Show less
-
-
-
BD
-
United States
-
Medical Equipment Manufacturing
-
700 & Above Employee
-
Information Technology Leadership Development (ITLP) Intern
-
Jun 2016 - Aug 2016
• Audited internal databases to find opportunities for cost savings and improve clarity of past and ongoing project compliance • Implemented live Qlikview dashboards to consolidate metrics for all projects, and identified potential for over $10,000’s in savings by flagging duplicate licenses and solutions • Performed 50 hours of solution assessment on EA management suites, allowing 5-person EA team to devote more hours to top priority legacy system overhaul • Audited internal databases to find opportunities for cost savings and improve clarity of past and ongoing project compliance • Implemented live Qlikview dashboards to consolidate metrics for all projects, and identified potential for over $10,000’s in savings by flagging duplicate licenses and solutions • Performed 50 hours of solution assessment on EA management suites, allowing 5-person EA team to devote more hours to top priority legacy system overhaul
-
-
-
iD Tech Camps
-
United States
-
Education Management
-
300 - 400 Employee
-
Instructor
-
Jul 2015 - Aug 2015
• Identified opportunity for Process Improvement in weekly software update procedure • Created Windows Homegroup network with file sharing capabilities to eliminate single-source bottleneck • Reduced update procedure time from 2-3 hours to under 1 hour • Identified opportunity for Process Improvement in weekly software update procedure • Created Windows Homegroup network with file sharing capabilities to eliminate single-source bottleneck • Reduced update procedure time from 2-3 hours to under 1 hour
-
-
Education
-
The Graduate School at Northwestern University
Master of Science - MS, Computer Engineering -
Northwestern University
Bachelor of Science (B.S.), Computer Engineering