Experience

MaxLinear

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Principal Design Automation Engineer

  • Jan 2022 - Present

  Principal Design Automation EngineerIP Development and VerificationTapeout Verification Lead SupervisorSenior RFIC Layout Designer

• Senior Staff Engineer, CAD & Physical Verification

  • Dec 2016 - Present

  CAD engineer and Physical Design Verification Worked on setting up and defining verification flows for various Foundry technologies. Lead coordinator and final Sign-Off for Tapeout procedures for every product of the company. IP Development and VerificationIn house circuit and layout design for custom IP for upcoming chip projects. Design translation and verification for cross foundry and technology tapeouts.

• Senior Staff Engineer - IP Development and Verification

  • Mar 2013 - Nov 2016

  IP Development and VerificationIn house circuit and layout design for custom IP for upcoming chip projects. Design translation and verification for cross foundry and technology tapeouts. Chip Top Level Floor planing and final tapeout verification for medium and large die SoC analog and digital chips.

• Senior Group Lead, RFIC Layout Designer

  • May 2006 - Feb 2013

  Responsible for SOC chip Top Level integration and verification.Interface with Back-end Physical Design team for Floor-planning SOC projects. Manage and recommend work schedules for analog layout projects.Train and Mentor new team members world-wide on RF analog layout and methodologies. Manage and assign work tasks for layout contractors in multiple sites.