Experience

CISPA Helmholtz Center for Information Security

• Germany
• Research Services
• 200 - 300 Employee

• Asynchronologist

  • Jan 2022 - Present



Senior researcher at the Max Planck Institute for Informatics in Saarbrücken, Germany

• Palo Alto, California and Saarbrücken, Germany

• Asynchronologist

  • 2019 - 2021

  I am working in the Theory of Distributed and Embedded Systems group where I am developing new circuits to help implement recent theoretical ideas on Metastability-Containing circuits. We have designed and fabricated two test chips. We are currently testing our second chip. I am working in the Theory of Distributed and Embedded Systems group where I am developing new circuits to help implement recent theoretical ideas on Metastability-Containing circuits. We have designed and fabricated two test chips. We are currently testing our second chip.



Sun Labs / Oracle Labs

• California

• Consulting Hardware Research Engineer

  • 1992 - 2019

  Asynchronous circuit and systems research and design. Synchronizer and Clock Domain crossing circuit design, analysis, and implementation in Sparc processors. Visualization and animation that aid in chip design. Formal Methods to identify synthesis generated glitch paths in large RTL modules. Asynchronous circuit and systems research and design. Synchronizer and Clock Domain crossing circuit design, analysis, and implementation in Sparc processors. Visualization and animation that aid in chip design. Formal Methods to identify synthesis generated glitch paths in large RTL modules.



Apple

• United States
• Computers and Electronics Manufacturing
• 700 & Above Employee

• Researcher in the Advanced Technology Group

  • 1987 - 1992

  Labyrinth FPGA circuit designer. Labyrinth FPGA circuit designer.