Experience

DeviceLab Inc.

• United States
• Medical Device
• 1 - 100 Employee

• Sr. SoC System Architecture- FPGA and embedded Firmware, Electrical Engineer

  • May 2022 - Present

  Successfully developed the Proof of Concept ( POC) for a proprietary conformal scanning laser system for the treatment of of retina degeneration. This project involves galvo control to steer the laser beam through optical chains to specific treatment locations of the retina. The success of this POC milestone grants the funding for subsequent phases by the investors. Also directly involve in the technical contributions for the winning of new business development efforts. Successfully developed the Proof of Concept ( POC) for a proprietary conformal scanning laser system for the treatment of of retina degeneration. This project involves galvo control to steer the laser beam through optical chains to specific treatment locations of the retina. The success of this POC milestone grants the funding for subsequent phases by the investors. Also directly involve in the technical contributions for the winning of new business development efforts.



Northrop Grumman

• Airlines and Aviation
• 1 - 100 Employee

• Sr. PRINCIPAL ASIC/FPGA DESIGNER

  • Jun 2019 - Apr 2022

  Work on multi-million gate ASICs and FPGAs architecture, emulator developments, and verification in the areas of digital communications, signal processing, network routing, embedded processors and switching applications for air and space applications. Work on multi-million gate ASICs and FPGAs architecture, emulator developments, and verification in the areas of digital communications, signal processing, network routing, embedded processors and switching applications for air and space applications.



UTC-N2-IMAGING SYSTEMS

• STAFF VIDEO SoC SYSTEM ENGINEER

  • Aug 2017 - May 2019

  • Video SoC System design using Xilinx Early-Acces ZYNQ Ultrascale+ MPSoC Embedded Vision (EV). • Multispectral Imaging sensors, Image Signals Processing IPs, Video Compressions (H.265, H.264) , Video recorder, Video Broadcast, UWB wireless communications • Video SoC System design using Xilinx Early-Acces ZYNQ Ultrascale+ MPSoC Embedded Vision (EV). • Multispectral Imaging sensors, Image Signals Processing IPs, Video Compressions (H.265, H.264) , Video recorder, Video Broadcast, UWB wireless communications



Rogerson Aircraft Corporation

• United States
• Business Consulting and Services
• 1 - 100 Employee

• Video Hardware Design Engineer- (Consultant)

  • May 2017 - Aug 2017

  • Multi-FPGA Designer for Networking- TCP/IP for video fusion applications. • Multi-FPGA Designer for Networking- TCP/IP for video fusion applications.



EXTRON ELECTRONICS, USA

• VIDEO HARDWARE DESIGN ENGINEER, Sr.

  • Sep 2013 - Dec 2016

  Involved in all phases of designing a multi-FPGA video system from scratch using 5 Xilinx FPGAs ( Embedded processor ZYNQ and KINTEX-7000 family) using Vivado SoC Development environment, drivers which are built and integrated with the Linux Kernel running on the Zynq ARM Processors. Designed “windows composition” video processing block, inter-FPGA custom link using Xilinx Aurora 64b/66b hi-speed ( 60 Gbps) serial link intellectual Property (IP). Video Interfaces used: Hi Definition Multimedia Interface ( HDMI), Digital Video Interface (DVI)-Serial Digital Interface(SDI), Bus protocol used:ARM AXI Bus. Show less



Fresenius Medical Care North America Corporate Research

• Electronics Design Engineer (contractor)

  • Apr 2012 - Jun 2013

  • Verilog development/verification and Hardware for FPGA based medical device application. Succesfully brought up many analog circuits/sensors( Op amp. Digital filter.ADCs, DACs, optical,Hall sensors, Solenoid valve, speaker, touch screen) and FPGA circuit designs (analog signal acquisition, control/Safety monitoring). Rearchitected the system communication port based on the specification document to enable multiple frame transactions with the cyclic redundancy check (CRC) capability. Developed the power management board tester using the National Instrument ( NI) Data acquisition( DAQ ) M Series NI 6259 box and the Labview Signal express software. These automation achievements have enabled the submission of the prototype to Food, Drug, and Cosmetic Act (FDA) 510K Show less



Boeing Satellite Systems

• United States
• Telecommunications
• 1 - 100 Employee

• Electronics Design and Analysis Engineer (contractor)

  • Feb 2012 - Mar 2012

  • Preliminary architecture design a sub-system using the Xilinx Virtex6 FPGA that emulates satellite functional blocks. • Preliminary architecture design a sub-system using the Xilinx Virtex6 FPGA that emulates satellite functional blocks.



Raytheon

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• Senior Multi-Disciplined Engineer II

  • Oct 2003 - Nov 2011

  •ASIC Obsolescence Program- retarget legacy AMCC ASICs to Honeywell’s HX2000 process. Modified the legacy simulation testbench to run “at system speed” from the AMCC legacy tester speed and read stimulus from vector file. •Developed reverse engineering timing analysis work flow from GDSII to Primetime using Cadence and Synopsys tools flow for the DARPA TRUST project. •Performed FPGA (Actel) timing analysis and managed Electronics Module (EM) Test procedures update team for an imaging satellite. •Developed Altera StratixII FPGA Reverse Engineering Binary Translator for the DARPA TRUST project. •Performed chip-to-chip Timing analysis at Board/Unit Levels for an imaging satellite project. •FPGA design/verification of a Hi-Speed application using SERDES and Rocket IO GigaBit Transceivers of the Xilinx Virtex IV FPGA . •FPGA design/verification of an Embedded SOC Architecture using Xilinx Virtex II Pro FPGA and the Embedded Developers Kit for the video processing application project. •Involved in the backend process of 3 FPGA-ASIC conversions. Main tasks are: TCL synthesis , Primetime, formality template scripts generation, some BIST, Boundary Scan/JTAG (IEEE Std 1149.1) for an imaging satellite. •Involved in the Verification of a R&D ASIC/VLSI Embedded and Networked SOC Architecture. Tasks include Test plan generation, PCI Bus Functional Model (BFM), CVS Makefile, Cadence simulator, VHDL bus monitor module, PSL, Perl, regression tests, vncheck linting, code coverage, Formality . •System integration debugging: Video Generation FPGA Debug, Board Debug using the “VXI Modular Instrumentation Platform Bus” interface. •Responsible for the conversion of a timing block from an ACTEL FPGA into an ASIC using Honeywell HX2000 cell library. •Designed RTL code for the Digital Signal Processing (DSP) block for the “space-frequency adaptive processor with time adaptive processing navigator “ (SFAP-T) FPGA ( Xilinx- Virtex-II pro). Show less



Northrop Grumman Corporation

• United States
• 1 - 100 Employee

• SENIOR TECHNICAL STAFF MEMBER

  • Jul 2003 - Oct 2003

  •Responsible for providing technical support for Engineering CAD tool, developing Digital ASIC design processes and tool automation . •Responsible for providing technical support for Engineering CAD tool, developing Digital ASIC design processes and tool automation .



APPLIED MICRO CIRCUITS CORPORATION

• United States
• Computer Hardware Manufacturing

• STAFF DESIGN ENGINEER

  • Jan 2001 - Jul 2002

  •Designed and debugged “the mapping of the 8B/10B client signal into SONET” Application Specific Standard Products (ASSP) used for the transport and the termination of STS-3/12/48/192 SONET data. •Designed the RTL code (Verilog), wrote test stimulus (VERA) for block level verification, instantiated the blocks into the top-level chip and assisted in the top-level verification. •Integrated code coverage tool (CoverMeter) with functional coverage (VERA) into VCS to measure the completeness of regression tests based on test plans. •As part of the chip-level verification environment development, wrote several Bus Functional Models (BFMs) using both Specman-e and Verilog languages. Also performed chip-level verification of different SONET blocks against specification requirements. Show less



Hewlett-Packard

• United States
• Information Technology & Services
• 300 - 400 Employee

• RESEARCH & DEVELOPMENT HARDWARE DESIGN ENGINEER

  • Jun 1994 - Jan 2001

  •Performed ASIC design, board design, and project management from concepts through manufacturing release of photographic printers. •Responsible for the design, verification, synthesis, and test vector generation for the following ASIC functional blocks: oDMA Controller/Arbiter in an embedded ARM 940T processor ASIC architecture. oMatrix Transform and Data Map/LookUp in an embedded Coldfire processor ASIC architecture. oThe Serial IO block to support the interASIC /interprocessor (ColdFire) Communication. •Performed emulation on ARM940T Logic Module, Quickturn, Xilinx FPGA board, and Chip Express board. •Familiar with HP2928A PCI analyzer/exerciser: Used this analyzer/exerciser to debug an embedded 33MHZ PCI based test system which make use of an Altera Flex 10K device with Altera PCI core. •Wrote C models for the Matrix Transform and Data Map/LookUP blocks for hardware implementation. •Leveraged and integrated the scanner (lamp-ballast controller) and printer (stepper-motor) analog driver boards and developed their functional test fixtures for the first consumer scanner/copier product. •Visited and selected vendors, support product qualification and testing process through Manufacturing release. Show less



PROCESS UNLIMITED

• United States
• Chemical Manufacturing

• PROJECT ENGINEER

  • Jun 1991 - Jan 1993

  •Developped Programmable Logic Controller (PLC) program and communication for automation and data acquisition projects. •Worked with customers from project scope, through design, implementation, and start-up. •Analyzed and tested PLC program and communications (DF1, MODBUS, DH485 protocols). •Retrofitted instrumentation system, used Man-machine interface (MMI) software (Wonderware, ICOM MM1500), wrote Operation Manuals of installed control systems. •Developped Programmable Logic Controller (PLC) program and communication for automation and data acquisition projects. •Worked with customers from project scope, through design, implementation, and start-up. •Analyzed and tested PLC program and communications (DF1, MODBUS, DH485 protocols). •Retrofitted instrumentation system, used Man-machine interface (MMI) software (Wonderware, ICOM MM1500), wrote Operation Manuals of installed control systems.