hiroshi kamisaka

Synapse Japan Executive Director at Synapse Design Inc.
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Contact Information
us****@****om
(386) 825-5501
Location
Los Gatos, California, United States, US
Languages
  • English Native or bilingual proficiency
  • Japanese Native or bilingual proficiency

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Experience

    • United States
    • Semiconductors
    • 500 - 600 Employee
    • Synapse Japan Executive Director
      • Aug 2018 - Present

      Establish Synapse Japan KK from scratch & handle immigration process

    • Program Director for Japanese Customers
      • Feb 2017 - Present

      Work for Japanese Customers Semiconductor (digital) design along with Synapse Vietnam team.Achieve $4M(VN price)=$20M(US price) business for 3years from scratch with Vietnam engineers.Achieve Semiconductor design work & business along with different country engineers & different way of thinking.

    • Senior Design Manager
      • May 2011 - Present

      DDR3,4 design with very small clock skew (5ps) data skew (15ps) with 16nm design for Broadcom's micro processor design work. Top level design & Block level designMany customer design consultant : TI, LSI logic, BroadCom, Cadence, etc... Consultant for SOC design tool and design flow methodology, Managerial skills, IP macro design

    • United States
    • Software Development
    • 700 & Above Employee
    • Senior Consulting Engineer
      • Jul 2010 - May 2011

      Sr Consultant engineer at Viragelogic and Synopsys IP macro design with ICC and Calibre Sr Consultant engineer at Viragelogic and Synopsys IP macro design with ICC and Calibre

    • United States
    • Software Development
    • 700 & Above Employee
    • Senior Consulting Engineer
      • Jan 2002 - Nov 2008

      Drove successful ASIC design engagements at Cisco, Toshiba America, Fujitsu Microelectronics America, Fujitsu Japan, NEC Europe, NEC Japan, and Renesas as a resident ASIC design expert in Cadence’s IC Digital Product Customer Driven R&D Group. These pilot design projects helped to develop user affinity for Cadence’s “SoC Encounter” ASIC implementation tools which helped the company win additional tool business. Drove adoption of new technologies such as SSTA and DFM/DFY in TSMC and Japanese foundries including the STARC consortium. Show less

    • Senior Consulting Engineer
      • Aug 2001 - Jan 2002

      Consult R&D to improve tool feature and support Toshiba america, KME(Kawasaki micro electronics), MITSUBISHI semiconductor and Fujitsu. Consult R&D to improve tool feature and support Toshiba america, KME(Kawasaki micro electronics), MITSUBISHI semiconductor and Fujitsu.

    • Computer Hardware Manufacturing
    • 1 - 100 Employee
    • Senior Consulting staff Engineer
      • Dec 1999 - Aug 2001

      Defined hierarch design flow and designed one of the most aggressive 90nm chip designs (18mmx18mm) utilizing flip chip design. The chip included a very high speed (~1Ghz) interface for Intel 64bit microprocessor to handle multiple power/ground signals. Developed high speed design flow and managed the relationships with Fujitsu Computer and Fujitsu Semiconductor. Consulted how to operate document control and developed the high speed design flow for the above design. Contact person among Fujitsu semiconductor, Fujitsu computer and HAL computer system group. Show less

    • IT Services and IT Consulting
    • 700 & Above Employee
    • Project Manager
      • Apr 1998 - Aug 2001

      Became Project Manager and managed around 40 people engineers. (Hardware engineers and BIOS engineers). Managed Intel Architecture system design (from project start through hardware design to supporting sales)

    • Technical Engineer
      • Apr 1981 - Mar 1998

      Joind Fujitsu Computer Division (Small office Computer system) design work for System board design, ASIC design, Microprocessor design, System Simulation design and Organize ISO2001 document control.

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