Experience

SiFive

• United States
• Semiconductor Manufacturing
• 400 - 500 Employee

• Senior Staff Engineer

  • Oct 2022 - Present



Samsung

• Bangalore

• Senior Staff Engineer

  • Sep 2018 - Feb 2023

  CPU Verification: Bring up of GIC600 VIP. SPI/PPI/LPI verification with/without CPU. Basic coherency verification. CPU to DRAM request testing. CPU DVFS testing. Bus Verification: All legal and ill-legal access. Performance, latency and Outstanding requests measurements. Request properties override. Parallel accesses from all masters to all slaves in the SoC. CPU Verification: Bring up of GIC600 VIP. SPI/PPI/LPI verification with/without CPU. Basic coherency verification. CPU to DRAM request testing. CPU DVFS testing. Bus Verification: All legal and ill-legal access. Performance, latency and Outstanding requests measurements. Request properties override. Parallel accesses from all masters to all slaves in the SoC.



NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Senior Verification Engineer

  • Jun 2014 - Aug 2018

  Safety verification of GPU using Synopsis Z01X : Created FIDM (fault injection and diagnostic manager) for redundant execution and machine check of GPU. Created fault simulation flow for GPU. Ran fault simulations for different IP's of GPU. Verification of Floor sweeping logic for CPU, GPU and Computer vision logic at SoC. Pre and Post silicon verification of Clocks logic in CPU: Clocks routing in CPU cluster. Switching of clock source between different plls in CPU cluster. Clock gating for power saving. Automatic frequency and voltage switching based on CPU load. Verification of security block in debug logic. Verification of package connections with port connections. Verification of SMMU using UVM environment. Added verification components to emulate memory which responds to page table walk requests. Wrote verification components to do random invalidations and sync using coherency channel of ACE interface Show less



LSI, an Avago Technologies Company

• Semiconductor Manufacturing
• 700 & Above Employee

• ASIC DvDs Engineer 2

  • Apr 2013 - Jul 2014

  Verificaiton of DMA Engine for Ethernet IP using Designware AHB UVM VIP. Verification of memories with repair logic using UVM. Wrote function coverage. Verificaiton of DMA Engine for Ethernet IP using Designware AHB UVM VIP. Verification of memories with repair logic using UVM. Wrote function coverage.



Qualcomm

• United States
• Telecommunications
• 700 & Above Employee

• Engineer

  • Jul 2010 - Apr 2013

  Verification of USB, HSIC using NSYS vip. Verification of USB3 using NSYS vip. Verification of DMA engine at SoC level. Verification of LPDDR3 using Denali memory models. Verification of debug logic in modem and verification of interrupt connectivity using assertions. Verification of USB, HSIC using NSYS vip. Verification of USB3 using NSYS vip. Verification of DMA engine at SoC level. Verification of LPDDR3 using Denali memory models. Verification of debug logic in modem and verification of interrupt connectivity using assertions.