Experience

Precision Innovations Inc

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Distinguished Engineer

  • Feb 2023 - Present



Dexterity, Inc.

• United States
• Software Development
• 100 - 200 Employee

• Software Architect

  • Dec 2020 - Feb 2023

  System+ Software architecture, implementation and optimization for full stack next gen robotics solutions including CV and ML. System+ Software architecture, implementation and optimization for full stack next gen robotics solutions including CV and ML.



Cadence Design Systems

• United States
• Software Development
• 700 & Above Employee

• Senior Software Architect (HSV Advanced Product Development)

  • Feb 2017 - Dec 2020

  - Technical leader for overall Palladium System Software managing terabytes of data between heterogeneous architectures (x86/proprietary parallel SOCs/custom switch fabric)- Chip bringup and development of next generation Palladium products- Responsible for coding major modules, setting coding standards/process and leading junior team members in a global team.- Delivered numerous performance and scalability improvements on existing legacy products by identifying non-disruptive improvements in existing products. Used the information to also improve the architecture of future products (software and hardware).- Designed, developed and tested all chip-gating product features for the next generating emulation platform. Found several RTL bugs through platform development on pre-silicon system-level emulation, significantly reducing tape-out risk.- Key developer for performance, stability and memory improvement for extremely large emulation jobs (up to 9B gate designs).- Optimized performance and memory usage on Palladium Z1 emulation hardware. * Reduced memory by 90% for the Palladium Z1 system manager. * Increased multi-job throughput by 2x by optimizing hardware access * Increased download throughput by 2x for large designs.- Designed a scalable data model for system telemetry.- Supporting key customers with enhancement requests and technical support

• Software Architect (Virtuoso Liberate Characterization Engine)

  • Feb 2012 - Feb 2017

  - Designed and developed the next generation characterization engine for throughput and compute efficiency improvements. Scaled the application from running on 1 machine (for large cells) to running on hundreds of machines (a few thousand cores). Implemented robust error handling and auto recovery. - Implemented auto-scaling and load balancing.- Enhanced and optimized the in-memory interface to Spectre for 22nm and lower process models.- Designed and implemented a cloud characterization solution using AWS ECC and AWS S3.- Delivered unified multi-corner solution for better job management, throughput and usability.- Worked directly and closely with 6 of the top 10 (and 10 of the top 20) Semiconductor Vendors to make the product successful under tight deadlines.- Optimized key legacy algorithms for threading, lower memory and high performance.

• Software Architect (Cadence Encounter Digital Implementation System)

  • Sep 2006 - Jan 2012

  - Worked on distributed processing and multi-threading applications within the flagship chip design suite as well as all issues related to software performance.- Designed a distributed processing API and infrastructure for use by different teams within the company including timing, pre and post route optimization.- Provided a thread-safe API to the design database for various engines.- Worked with multiple teams on issues such as performance profiling, lock contention, efficient threaded implementation in the presence of critical code and memory management.- Evangelized the merits of distributed processing for performance within the company and helped groups across Cadence understand and incorporate distributed processing within their code.



Rio Design Automation

• Software Development
• 1 - 100 Employee

• Member of Technical Staff

  • Jun 2004 - Sep 2006

  - Database infrastructure for a hierarchical chip package co-design tool. - Design and implementation of a wire bond IO planning product. - Customer benchmarks and demos resulting in sales to major semiconductor vendors. - Software operations (builds, QA, porting, bugs database, tutorial/demo development etc.). - Database infrastructure for a hierarchical chip package co-design tool. - Design and implementation of a wire bond IO planning product. - Customer benchmarks and demos resulting in sales to major semiconductor vendors. - Software operations (builds, QA, porting, bugs database, tutorial/demo development etc.).



Ciranova Inc.

• Campbell, CA

• Member of Technical Staff

  • Dec 2002 - Jun 2004

  • Fast parasitic estimation. • Implementation of various analyses engines (Electromigration, Process gradient, and parasitic constraints) plus related GUI development in Qt. • Designing and writing 2 way interfaces to 3rd party tools (Calibre-DRC/Calibre-XRC/Itools router/Pulsic Router). Writing TCL interface commands for tool operations, Solaris/Linux ports, Integration of KDExecutor for automated GUI testing, • Spice import/export with controllable parasitic details. • Fast parasitic estimation. • Implementation of various analyses engines (Electromigration, Process gradient, and parasitic constraints) plus related GUI development in Qt. • Designing and writing 2 way interfaces to 3rd party tools (Calibre-DRC/Calibre-XRC/Itools router/Pulsic Router). Writing TCL interface commands for tool operations, Solaris/Linux ports, Integration of KDExecutor for automated GUI testing, • Spice import/export with controllable parasitic details.



Cadence Design Systems

• United States
• Software Development
• 700 & Above Employee

• Senior Member of Consulting Staff

  • Aug 1998 - Nov 2002

  - Promoted twice within the first 3 years and recognized for exceptional performance. - Improved the performance of timing driven placement within SOC-Encounter. - Technical lead (06/01-06/02) for placement group. Mentored new hires and other group members. - Enhanced timing driven placement and optimization features based on customer requests. - Worked on harmonizing tool behavior on multiple 32 and 64 bit platforms. - Designed and developed a distributed regression testing system to test placement, routing and timing analysis within the design flow across multiple platforms. - Technical lead (8/99-6/00) for the Static Timing Analysis solution for Digital IC products - Worked on a major rewrite of the core timing engine algorithms to support “through” timing exceptions. - Worked on memory and performance analysis and optimization and integration for timing driven flows. - Worked with major semiconductor design houses like NEC, Siemens, Fujitsu, AMD and Toshiba



Digital Equipment Corporation (USA)

• United States
• Computer Hardware Manufacturing
• 1 - 100 Employee

• Software Engineer

  • May 1996 - Aug 1998

  - Owner of the circuit classification and manipulation library, which was used by in-house static timing verification, design rule verification, race analysis and power estimation/optimization tools. - Responsible for specification, design, implementation and support of schematic and layout verification rules including crosstalk analysis and multiple supply domain rules for Intel StrongARM SA1100/SA1500 and ALPHA-AXP 21264/21364/21464 high performance microprocessors. - Outstanding achievement award for CAD support to StrongARM SA-1100 (June 1997).