Experience

SiFive

• United States
• Semiconductor Manufacturing
• 400 - 500 Employee

• Vice President

  • 2022 - 1 year

  San Francisco Bay Area



Samsung Electronics America

• United States
• Computers and Electronics Manufacturing
• 700 & Above Employee

• Director

  • 2016 - 2022

  San Francisco Bay Area Managing development of innovative low power, high performance Graphics Processor IP for next generation mobile devices.



AMD

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Director of Engineering

  • 2009 - 2015

  Austin, Texas Area • SOC Director leading the cross functional engineering team that developed the latest generation of AMD flagship client Notebook & Desktop processors - Trinity and Richland APUs as well as a custom APU for the semicustom BU • Led the development of engineering execution plan and tightly managed the trade-offs of scope/schedule/cost to hit program schedule within a week of the target set 2 years earlier • Lead all phases of SOC development from architecture to Physical Design from start… Show more • SOC Director leading the cross functional engineering team that developed the latest generation of AMD flagship client Notebook & Desktop processors - Trinity and Richland APUs as well as a custom APU for the semicustom BU • Led the development of engineering execution plan and tightly managed the trade-offs of scope/schedule/cost to hit program schedule within a week of the target set 2 years earlier • Lead all phases of SOC development from architecture to Physical Design from start to tapeout of production rev • Includes SOC Architecture, RTL Design, Verification, DFT, Circuits, Physical Design, and support for silicon validation test plan development, and post silicon validation • Drove Validation Test Plan development, planning & execution of silicon validation readiness for Debug tools, Infrastructure, diagnostics, BIOS, software and ATE patterns using hardware emulation, simulation, and hardware test vehicles for Trinity • Worked closely with IP teams to define performance and low power requirements • Worked with Design, CAD and other stake holders to revamp SOC Design methodology based on the feedback from lessons learnt initiatives from past projects Show less



AMD

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Manager

  • 1999 - 2008

  Austin, Texas Area • Successfully taped out the 45 nm Dachshund processor for Notebooks and value desktops and Blood Hound processor for mainstream desktops • As the Silicon Eval Lead, led the development of Validation Test Plans for silicon validation of Dachshund and Blood Hound microprocessors and drove the post silicon validation and prepared the products for mass production • Worked with the BU and developed the concept & definition for the 6 core Pharaoh Hound processor with APM technology reusing… Show more • Successfully taped out the 45 nm Dachshund processor for Notebooks and value desktops and Blood Hound processor for mainstream desktops • As the Silicon Eval Lead, led the development of Validation Test Plans for silicon validation of Dachshund and Blood Hound microprocessors and drove the post silicon validation and prepared the products for mass production • Worked with the BU and developed the concept & definition for the 6 core Pharaoh Hound processor with APM technology reusing existing IP for the enthusiast desktop segment which helped generate >$300 million of incremental revenue • SOC Physical Design Lead for 65 nm Griffin – first AMD product targeted exclusively for the Notebook market. Built the Austin North SOC team from scratch and successfully delivered the product on schedule and supported through production release till end of life. • Drove several design initiatives to achieve faster design cycles, including the adoption of industry standard floorplanning tool & methodology, wider use of synthesis & APR and automated overlay creation for all AMD products • Led the design of core logic chipsets for AMD’s K7 (Athlon) and K8 (Opteron) microprocessors. These included the IGD4 DDR North Bridge for K7 and AGP 3.0 (Client) and PCIX (Server) HyperTransport tunnels for the K8 family Show less



AMD

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Member of Technical Staff / Design Manager

  • 1993 - 1998

  Austin, Texas Area • Led the design of two Embedded System-On-Chip processors (Elan and Aspen) based on the X86 architecture for embedded applications; both chips taped out on schedule & were first pass functional • Developed and maintained implementation plans and design schedules; tracked key implementation issues and drove them to closure • Led the startup of a remote design center in Singapore & mentored the site to a team capable of executing derivative design projects independently • Designed I/O… Show more • Led the design of two Embedded System-On-Chip processors (Elan and Aspen) based on the X86 architecture for embedded applications; both chips taped out on schedule & were first pass functional • Developed and maintained implementation plans and design schedules; tracked key implementation issues and drove them to closure • Led the startup of a remote design center in Singapore & mentored the site to a team capable of executing derivative design projects independently • Designed I/O buffers, programmable termination circuits, clock distribution units and JTAG test interface Show less



Ross Technology

• Senior Design Engineer

  • 1990 - 1993

  Austin, Texas Area • Member of team of 30 engineers that developed the first superscalar implementation of the Sparc architecture – the HyperSparc microprocessor • RTL modeling and verification, logic design and optimization, circuit design and layout for the Bus Interface, IO pads & pad ring, and JTAG test interface units. Wrote SPARC assembly language test vectors for full chip functional verification.