Experience

Encore Semi, Inc.

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Sr Design Verification Engineer

  • Oct 2016 - Present

  Sep 2021 - Present: Consulting at BAE Systems Worked on test plan creation and verifying the registers on 3 different FPGA designs in Firetip program 2016-2021: Consulting at Global Foundries/AveraSemi/Marvell Technology, Inc Worked on multiple turnkey projects with ARM CPU/NIC/IPs performing various verification activities using UVM based TBs. Jan 2021 - Aug 2021 : ITAR project Developed a generic project flow for integrating Jasper formal verification apps, UNR and CONN Implemented them in 4 different subsystems and got the coverage numbers up significantly 2020 - 2021: Proj M Verification of LPDDR4 subsystem including MC/PHY Created the UVM TB from scratch using Cadence AXI/APB VIPs Implemented and verified various modes of 1d training sequence by writing the sequences in UVM Wrote sequences/tests for verifying different power saving modes 2019 - 2020: Viaphy3 Viaphy3 ASIC is an ARM based CPU subsystem meant for Satellite applications Implemented a TB flow for handling encrypted RTL sims and made periodic releases to the customer Reproduced lot of customer issues in the TB and got the fixes released to them Responsible for all the top level SoC TB periodic updates/releases to the team Debugged all the regression failures and got the issues resolved 2017 - 2019: ITAR project Full verification of adding a brand new AHB master interface to the ASIC including SB development Added a reset mechanism in UVM while the DUT is processing sequences Did debug of regression failures and Implemented a complete coverage collection/closure flow in the TB 2016 - 2018: Gin DP/VP GIN DP/VP are two SoCs with ARM IPs designed for the next generation of mobile networks infrastructure Responsible for SoC level UVM TBs focused on verifying various IP integrations in both the SoCs Complete ownership of verification for various instances of DMA IPs in the top level TB, Gin DP Full responsibility of verifying the GPU IP in the Soc TB in Gin VP Show less



Seagate Technology

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Staff Verification Engineer

  • Sep 2014 - May 2016

  Worked on the verification of an FPGA which is part of an NVMe acceleration card that interfaces to the host using PCI-e over NVMe and is designed to work with 1866 MHz DDR3 SDRAM. -Developed the UVM based testbenches for the blocks message center, extended memory subsystem (includes DDR3,AMBA AXI3/APB) from ground up. -Coded and verified all parts/phases of the testbench including stimulus, scoreboard, test cases, debugging and closing the code coverage. Worked on the verification of an FPGA which is part of an NVMe acceleration card that interfaces to the host using PCI-e over NVMe and is designed to work with 1866 MHz DDR3 SDRAM. -Developed the UVM based testbenches for the blocks message center, extended memory subsystem (includes DDR3,AMBA AXI3/APB) from ground up. -Coded and verified all parts/phases of the testbench including stimulus, scoreboard, test cases, debugging and closing the code coverage.



LSI, an Avago Technologies Company

• Semiconductor Manufacturing
• 700 & Above Employee

• Staff Verification Engineer/Verification Lead

  • Jun 2008 - Aug 2014

  Jan 2011 - Aug 2014 : Staff Verification Engineer, NCD -------------------------------------------------------------------------------- Worked on the verification of Axxia, a series of advanced communication processor SoCs aimed at meeting the increased performance requirements of next generation mobile/enterprise networks. - Developed all components of the System/tree memory test benches with AXI3 interfaces and using SV&LVM - Verified them including the DDR3 LSI phy training in simulation. Closed the code/functional coverage as well. June, 2008 - Dec 2010: Verification Lead (Tarari Group) -------------------------------------------------------------------------------- Verification of Lanai and Maia that are the next generation content security processors with regular expression/other type of engines. - Led and managed Lanai verification effort/team by scoping the effort, Gantt preparation, hiring contractors, dayto-day management and providing direction to the entire verification team - Performed the individual tasks like test bench coding in SV&VMM, setting up tools/flow, test writing/debugging - Setup regression flow, scripting and first level debug of the failures Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Verification Lead

  • Jan 2006 - Feb 2008

  Verification of Crestline, Cantiga and Gen6 that are Intel’s next-generation chipset products that contain integrated graphics, GPU that supports Microsoft DX10. - Leadership role for the verification of interrupt mechanism in advanced scheduler mode for 3D graphics - Implemented a complex run environment successfully which includes writing the testbench in Verilog at both pipe and Full chip level, writing Perl scripts for various tasks - Wrote/Executed the test plan by generating the directed/random tests and collecting coverage Show less



NXP Semiconductors

• Netherlands
• Semiconductor Manufacturing
• 700 & Above Employee

• Project Lead and Verification Engineer

  • Apr 2000 - Oct 2005

  Verification/Ownership of delivering multiple video processing blocks of SoCs/IPs/ASICs like MBVP,CPIPE that are used in HDTVs. -Management of IP emulation including the releases from the software (driver) group -Project leadership with focus on project planning and management, handling of globally distributed multi-site sub-contracts, periodic database releases to the chip integration team -RTL integration of sub-modules (both Verilog&VHDL) and synthesis, STA, writing module specs -Verification of various sub-blocks of the IP - Developing the perl-based verilog test bench, generating the tests (directed and random) and debugging of the tests against a reference model in C/C++ to root-cause the problem - Writing test-plan, and running regression of the above test-suites, meeting coverage goals - Delivering the IP via quality simulations (RTL and gates), emulation and collecting coverage - Formal verification via Verplex, metal fixes for bugs in revB and revC Show less