Experience

Cysic

• United States
• Blockchain Services
• 1 - 100 Employee

• Cryptography Researcher

  • Oct 2023 - Present



Algorand Technologies

• United States
• Software Development
• 1 - 100 Employee

• Software Engineer

  • Jul 2021 - Sep 2023



University of Virginia

• United States
• Higher Education
• 700 & Above Employee

• Research Assistant

  • Jan 2020 - May 2021

  Worked on research problems in applied cryptography, advised by Prof. David J. Wu. We designed and implemented a concrete-efficient post-quantum zkSNARK (zero-knowledge succinct non-interactive argument of knowledge) from lattice-based cryptographic assumption. The proof size of our construction is 10.3x smaller than previous post-quantum candidates. Compared to previous lattice-based zkSNARK, we achieved a 42x reduction in proof size and 60x reduction in prover time, all while achieving… Show more Worked on research problems in applied cryptography, advised by Prof. David J. Wu. We designed and implemented a concrete-efficient post-quantum zkSNARK (zero-knowledge succinct non-interactive argument of knowledge) from lattice-based cryptographic assumption. The proof size of our construction is 10.3x smaller than previous post-quantum candidates. Compared to previous lattice-based zkSNARK, we achieved a 42x reduction in proof size and 60x reduction in prover time, all while achieving a much higher level of soundness. Compared to the pre-quantum zkSNARK with smallest proof size by Groth (Eurocrypt 2016), our proof size is 131x larger, but our prover and verifier time are 1.2x and 2.8x faster, respectively. We had a paper published in ACM CCS 2021, Seoul, Korea. Show less Worked on research problems in applied cryptography, advised by Prof. David J. Wu. We designed and implemented a concrete-efficient post-quantum zkSNARK (zero-knowledge succinct non-interactive argument of knowledge) from lattice-based cryptographic assumption. The proof size of our construction is 10.3x smaller than previous post-quantum candidates. Compared to previous lattice-based zkSNARK, we achieved a 42x reduction in proof size and 60x reduction in prover time, all while achieving… Show more Worked on research problems in applied cryptography, advised by Prof. David J. Wu. We designed and implemented a concrete-efficient post-quantum zkSNARK (zero-knowledge succinct non-interactive argument of knowledge) from lattice-based cryptographic assumption. The proof size of our construction is 10.3x smaller than previous post-quantum candidates. Compared to previous lattice-based zkSNARK, we achieved a 42x reduction in proof size and 60x reduction in prover time, all while achieving a much higher level of soundness. Compared to the pre-quantum zkSNARK with smallest proof size by Groth (Eurocrypt 2016), our proof size is 131x larger, but our prover and verifier time are 1.2x and 2.8x faster, respectively. We had a paper published in ACM CCS 2021, Seoul, Korea. Show less



UM-SJTU Joint Institute, Shanghai Jiao Tong University

• China
• Higher Education
• 1 - 100 Employee

• VE 482 (Operating System) Teaching Assistant

  • Sep 2018 - Dec 2018

  Led weekly lab sessions and recitations classes, built a grading server for student coding assignments, held weekly office hours and graded midterms and finals.

• VE 216 (Signals and Systems) Teaching Assistant

  • May 2018 - Aug 2018

  Led weekly lab sessions and recitations classes, assisted instructor in producing problem sets and exams, graded student assignments, held weekly office hours and graded midterms and finals.



UM-SJTU Joint Institute, Shanghai Jiao Tong University

• China
• Higher Education
• 1 - 100 Employee

• Research Asssistant

  • Aug 2017 - Mar 2018

  Worked in Emerging Computing Technology Laboratory in SJTU on research problems in approximate computation and error-tolerant circuit synthesis. We built a rapid logic circuit simulator by translating target circuit into C++, and measuring performance over compiled code. Our simulator took advantage of CPU instruction pipelining and achieved over 5000× speed-boost than naive implementations. Worked in Emerging Computing Technology Laboratory in SJTU on research problems in approximate computation and error-tolerant circuit synthesis. We built a rapid logic circuit simulator by translating target circuit into C++, and measuring performance over compiled code. Our simulator took advantage of CPU instruction pipelining and achieved over 5000× speed-boost than naive implementations.