Experience

5 Systems

• Hungary
• Semiconductor Manufacturing
• 1 - 100 Employee

• Principal Engineer, Co-Founder

  • Jan 2021 - Present

  Our mission is to provide the best possible services in EDA with highly talented and experienced engineers. Dedicated team solving the real hard problems let it be Digital Design, Verification or Embedded SW. Our mission is to provide the best possible services in EDA with highly talented and experienced engineers. Dedicated team solving the real hard problems let it be Digital Design, Verification or Embedded SW.



AIStorm INC

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Principal Digital Design and Verification Engineer

  • Jul 2019 - Jan 2021

  Principal engineer reponsible for AIStorm's AI on Chip mix-signal digital design an verification. Intensive role required experties in myriad of areas. My main activites were ranging from architecure defintion, digital flow development and digital design/verification to all the way to backend spiced with some FPGA. Principal engineer reponsible for AIStorm's AI on Chip mix-signal digital design an verification. Intensive role required experties in myriad of areas. My main activites were ranging from architecure defintion, digital flow development and digital design/verification to all the way to backend spiced with some FPGA.



Cadence Design Systems

• United States
• Software Development
• 700 & Above Employee

• Principal Application Engineer

  • Jul 2014 - Jun 2019

  Responsible for providing support/training/services for JasperGold platform working mainly with ustomers in EMEA region. Responsible for providing support/training/services for JasperGold platform working mainly with ustomers in EMEA region.



Jasper Design Automation

• United States
• Software Development
• 1 - 100 Employee

• Field Application Engineer

  • Jul 2013 - Jun 2014

  Field Application Engineer at Jasper Design Automation. Field Application Engineer at Jasper Design Automation.



Duolog Technologies

• United Kingdom
• Software Development
• 1 - 100 Employee

• Senior Verification Engineer

  • Feb 2013 - Jun 2013

  Design service work as a senior verification engineer for Movidius.

• Senior Verification Engineer

  • Nov 2011 - Feb 2013

  Design service work as a senior verification engineer for Texas Instruments France.



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Specman Consultant

  • Aug 2007 - May 2011

  I was responsible for creating, enhancing and updating new and existing Specman verification environments. The role also included verification planning for coverage closure and developing new eVCs, test-cases and also running regressions. As a verification leader I also managed/coordinated small groups of 2-4 verification engineers. Projects: AXI Bridge, DigRF RFIC and BBIC, DSP Subsystem, System level verification and many more) I was responsible for creating, enhancing and updating new and existing Specman verification environments. The role also included verification planning for coverage closure and developing new eVCs, test-cases and also running regressions. As a verification leader I also managed/coordinated small groups of 2-4 verification engineers. Projects: AXI Bridge, DigRF RFIC and BBIC, DSP Subsystem, System level verification and many more)



Duolog Technologies Ltd

• Verification Engineer

  • Jul 2005 - Aug 2007

  Design service work as a verification engineer for Texas Instruments France. My role was to develop verification environments for RTL and Gate level simulations using Specman, running regressions and coverage analysis (VENCOCP, Camera Subsystem). As a verification leader I was also responsible to create project plans and verification strategy for coverage closure (Display Subsystem, Camera Subsystem ES2+ DSI PHY).

• IC Design Engineer

  • Aug 2004 - Jul 2005

  Design service work for Texas Instruments France. My role was to develop synthesizable Bus Functional Modules (SDI, SDI2, TRACE, CBUS, DBUS, DigRF, MODDATA) using VHDL/Verilog and create test-bench automation scripts using TCL/Perl. Did top level test-bench integration and project planning as project leader (SEDNA, OMAP2430C)