Gleb Zagliadin
lead engineer at Milandr- Claim this Profile
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Русский Native or bilingual proficiency
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English Limited working proficiency
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Bio
Experience
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Milandr
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Russian Federation
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Semiconductor Manufacturing
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1 - 100 Employee
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lead engineer
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Jan 2016 - Present
FPGA EDA flow (C++): - YOSYS setup; - backend data structures; - routing and placement delay models; - automatic port-pin assignment; - SA, min-cut, quadratic placement; - pathfinder router; - bitmap export; - export of simulation netlist; Guilty of current FPGA routing architecture. FPGA EDA flow (C++): - YOSYS setup; - backend data structures; - routing and placement delay models; - automatic port-pin assignment; - SA, min-cut, quadratic placement; - pathfinder router; - bitmap export; - export of simulation netlist; Guilty of current FPGA routing architecture.
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Software Developer
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Jul 2013 - Dec 2015
Test chip modules database development(PostgreSQL) and client application(Tcl\Tk), graphical EDA software log analyzer with cell timing information(C++\Qt), memory compiler framework(GUI - Java:Swing, core - C++, Java), Eclipse IDE plugins(xtext-based), perl/python scripts. Test chip modules database development(PostgreSQL) and client application(Tcl\Tk), graphical EDA software log analyzer with cell timing information(C++\Qt), memory compiler framework(GUI - Java:Swing, core - C++, Java), Eclipse IDE plugins(xtext-based), perl/python scripts.
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Associate Professor
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Jun 2009 - Jul 2013
Taught VLSI physical design automation. Taught VLSI physical design automation.
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EDA support engeneer
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Jun 2007 - Nov 2008
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Education
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Московский Государственный Институт Электронной Техники (Технический Университет) (МИЭТ)
Кандидат технических наук (Ph.D), Системы автоматизированного проектирования (EDA)