Experience

Milandr

• Russian Federation
• Semiconductor Manufacturing
• 1 - 100 Employee

• lead engineer

  • Jan 2016 - Present

  FPGA EDA flow (C++): - YOSYS setup; - backend data structures; - routing and placement delay models; - automatic port-pin assignment; - SA, min-cut, quadratic placement; - pathfinder router; - bitmap export; - export of simulation netlist; Guilty of current FPGA routing architecture. FPGA EDA flow (C++): - YOSYS setup; - backend data structures; - routing and placement delay models; - automatic port-pin assignment; - SA, min-cut, quadratic placement; - pathfinder router; - bitmap export; - export of simulation netlist; Guilty of current FPGA routing architecture.



Angstrem-T

• Software Developer

  • Jul 2013 - Dec 2015

  Test chip modules database development(PostgreSQL) and client application(Tcl\​Tk), graphical EDA software log analyzer with cell timing information(C++\​Qt), memory compiler framework(GUI - Java:Swing, core - C++, Java), Eclipse IDE plugins(xtext-based), perl/python scripts. Test chip modules database development(PostgreSQL) and client application(Tcl\​Tk), graphical EDA software log analyzer with cell timing information(C++\​Qt), memory compiler framework(GUI - Java:Swing, core - C++, Java), Eclipse IDE plugins(xtext-based), perl/python scripts.



National Research University of Electronic Technology

• Associate Professor

  • Jun 2009 - Jul 2013

  Taught VLSI physical design automation. Taught VLSI physical design automation.



Mikron JSC

• EDA support engeneer

  • Jun 2007 - Nov 2008