Giorgos Stanimeropoulos

Research And Development Engineer at Circuits and Systems Lab, University of Thessaly
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Contact Information
us****@****om
(386) 825-5501
Location
Thessaloniki, Central Macedonia, Greece, GR
Languages
  • English -

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Experience

  • Circuits and Systems Lab, University of Thessaly
    • Greece
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Research And Development Engineer
      • Jan 2023 - Present

  • Qualcomm
    • United States
    • Telecommunications
    • 700 & Above Employee
    • Engineer Intern
      • Jul 2022 - Nov 2022

      -Software engineering (2 projects) -Various internal flows of the DTech team -Software engineering (2 projects) -Various internal flows of the DTech team

  • Circuits and Systems Lab, University of Thessaly
    • Greece
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Software Engineer
      • Apr 2021 - Jul 2022

    • Research And Development Engineer
      • Nov 2019 - Jul 2022

    • Student Mentor
      • Jun 2020 - Oct 2020

      During Circuits and Systems Lab's annual summer internship, I supervised and supported two interns through their projects. One of the interns was assigned to create a Bookshelf HDL to LEF/DEF/Verilog converter, while the other was tasked with analyzing the hMetis clustering/partitioning tool.

  • University of Thessaly
    • Greece
    • Higher Education
    • 700 & Above Employee
    • Laboratory Assistant
      • Sep 2021 - Jan 2022

      During the fall semester of 2022, I was a laboratory assistant in the Digital Design course. Main tasks involved answering questions and grading students

    • Laboratory Assistant
      • Sep 2021 - Jan 2022

      During this period, I was a laboratory assistant in Programming I. Main tasks involved answering questions and grading students.

  • Circuits and Systems Lab, University of Thessaly
    • Greece
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Junior Software Engineer
      • Jun 2019 - Sep 2019

      During my summer internship, I developed a tool that estimates the wire congestion of a design using the half-perimeter bounding box algorithm. I also developed a basic API using TCL, as well as a GUI to showcase the design and the estimator's result using the GTK 2.0 library During my summer internship, I developed a tool that estimates the wire congestion of a design using the half-perimeter bounding box algorithm. I also developed a basic API using TCL, as well as a GUI to showcase the design and the estimator's result using the GTK 2.0 library

Education

  • University of Thessaly
    Master's degree, Electrical and Computer Engineering
    2018 - 2023
  • 1ο ΓΕΛ Κιλκίς
    19,9
    2015 - 2018

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