Gianmarco Dinelli

Digital hardware engineer at IngeniArs S.r.l.
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Contact Information
Location
Lucca, Tuscany, Italy, IT
Languages
  • Italiano -
  • Inglese -

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Experience

    • Italy
    • Computer Hardware
    • 1 - 100 Employee
    • Digital hardware engineer
      • Jan 2021 - Present
    • Italy
    • Mental Health Care
    • 100 - 200 Employee
    • PhD student
      • Oct 2017 - Jun 2021

      Main projects: -) Development of an FPGA hardware accelerator for a CNN, which was designed for a keyword spotting application. We started from the model implemented in a previous work for the Intel Movidius Neural Compute Stick. For our goals, we appropriately quantized such a model through a bit-true simulation, and we realized a dedicated architecture exclusively using on-chip memories. -) Design of an FPGA hardware accelerator for the CloudScout CNN. CloudScout is a project funded by the European Space Agency (ESA) targeting the development, and for the first time in-orbit demonstration, of a CNN-based algorithm for cloud detection. At the present state of the project, the inference is computed by an INTEL Myriad 2 VPU on-board the Physat-1 CubeSat. The aim of this project is to provide a benchmark between the Myriad 2 and our custom hardware accelerator designed for FPGAs. The comparison is made in terms of inference time, power consumption, space qualification, components and development cost. -) The aim of this project is designing, testing and implementing the SpaceFibre IP cor on different FPGA devices. SpaceFibre is an upcoming on-board high-speed communication protocol for space applications. It has been developed in collaboration with the European Space Agency to answer the growing data-rate requirement of satellite payloads such as Synthetic Aperture Radars and hyper-spectral imagers. SpaceFibre supports high data-rate payload data-handling (up to 6.25 Gb/s), operating both on copper cables and optical fibre. In particular, the SpaceFibre IP core has been designed including multi-lane communication, which allows to increase the maximum achievable data rate and enhance system robustness and reliability. The IP has been fully tested through a SystemVerilog and UVM environment, and it has been prototyped on different platforms, including radiation tolerant Microsemi RTG4 and COTS Xilinx devices such as the Zynq 7000 FPGA. Show less

Education

  • Università di Pisa
    Master’s degree, 110/110 cum Laude, Electronics Engineering
    2014 - 2017
  • Università di Pisa
    Bachelor’s degree, 110/110, Electronics Engineering
    2010 - 2014

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