Experience

Uniquify Inc

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Analog Design Manager

  • Dec 2014 - Present

   Work on DDRIO process: smic40ll, smic55ll, tsmc28hpm, tsmc28hpc, tsmc28hpc+, Samsung s28lpp, gf28slp, gf40lp, gf22fdx, tsmc40g, tsmc40lp  Responsible for pad frame floor-plan, power pattern, layout top level, EMIR verification, ESD estimation.  Bangap design.  Differential amplifier design.  DDRIO’s transmitter and receiver design  Responsible for both layout and schematic implementation.  Work on DDRIO process: smic40ll, smic55ll, tsmc28hpm, tsmc28hpc, tsmc28hpc+, Samsung s28lpp, gf28slp, gf40lp, gf22fdx, tsmc40g, tsmc40lp  Responsible for pad frame floor-plan, power pattern, layout top level, EMIR verification, ESD estimation.  Bangap design.  Differential amplifier design.  DDRIO’s transmitter and receiver design  Responsible for both layout and schematic implementation.



eSilicon

• United States
• Semiconductor Manufacturing
• 100 - 200 Employee

• Memory designer

  • Oct 2009 - Nov 2014

  2014  Work on DP SRAM finfet 16n of TSMC for Avago, responsible for function verification, characterization and timing verification. Optimize performance and power.  Build up LMFF tool with CAD team for generate critical path automatically. 2013  Work on DP SRAM process 20nm of Global Foundry for Intel, responsible for function verification, characterization and timing verification.  Working with CAD team to build LMFF tool which allowed building full instance from schematic… Show more 2014  Work on DP SRAM finfet 16n of TSMC for Avago, responsible for function verification, characterization and timing verification. Optimize performance and power.  Build up LMFF tool with CAD team for generate critical path automatically. 2013  Work on DP SRAM process 20nm of Global Foundry for Intel, responsible for function verification, characterization and timing verification.  Working with CAD team to build LMFF tool which allowed building full instance from schematic leafcell. 2011-2012  Responsible for pre-sales supports on supper high performance, ultralow power SRAM and high density ROM designs at nanometer technology nodes such as 28nm, 45nm and 65nm  Investigate and evaluate the design tool kits for embedded memory development  Perform the bitcell analysis for different type of bitcells at various process nodes to benchmark the design performance, power and area among process nodes. 2010 - 2011  Responsible for the characterization and timing verification for Supper Cache instances in MIPS processor  Perform the deep-dive studies to enhance the performance for the critical circuit to achieve higher performance for Supper Caches  Jointly investigate the design automation approach to estimate the performance, power and area trade off 2009-2010  Responsible for the high performance Integrated BIST verification for 45nm TCAM, SP and DP development including: o Perform design characterization including setup measurement, equation and do min-constraint. o Verified the circuits including the steps of functional verification, margin check which covers timing racing (pre-read margin, pre-charge overlap word line) o Carried out the QA phase, which includes linearity check, timing and power trend check.  Responsible for the development of automation tool based on visual basic to manage and filter data, plot chart to trend check and compare among PDKs from 90nm to 28nm Show less 2014  Work on DP SRAM finfet 16n of TSMC for Avago, responsible for function verification, characterization and timing verification. Optimize performance and power.  Build up LMFF tool with CAD team for generate critical path automatically. 2013  Work on DP SRAM process 20nm of Global Foundry for Intel, responsible for function verification, characterization and timing verification.  Working with CAD team to build LMFF tool which allowed building full instance from schematic… Show more 2014  Work on DP SRAM finfet 16n of TSMC for Avago, responsible for function verification, characterization and timing verification. Optimize performance and power.  Build up LMFF tool with CAD team for generate critical path automatically. 2013  Work on DP SRAM process 20nm of Global Foundry for Intel, responsible for function verification, characterization and timing verification.  Working with CAD team to build LMFF tool which allowed building full instance from schematic leafcell. 2011-2012  Responsible for pre-sales supports on supper high performance, ultralow power SRAM and high density ROM designs at nanometer technology nodes such as 28nm, 45nm and 65nm  Investigate and evaluate the design tool kits for embedded memory development  Perform the bitcell analysis for different type of bitcells at various process nodes to benchmark the design performance, power and area among process nodes. 2010 - 2011  Responsible for the characterization and timing verification for Supper Cache instances in MIPS processor  Perform the deep-dive studies to enhance the performance for the critical circuit to achieve higher performance for Supper Caches  Jointly investigate the design automation approach to estimate the performance, power and area trade off 2009-2010  Responsible for the high performance Integrated BIST verification for 45nm TCAM, SP and DP development including: o Perform design characterization including setup measurement, equation and do min-constraint. o Verified the circuits including the steps of functional verification, margin check which covers timing racing (pre-read margin, pre-charge overlap word line) o Carried out the QA phase, which includes linearity check, timing and power trend check.  Responsible for the development of automation tool based on visual basic to manage and filter data, plot chart to trend check and compare among PDKs from 90nm to 28nm Show less