Experience

Lucata

• United States
• Computer Hardware Manufacturing
• 1 - 100 Employee

• Senior FPGA Design Engineer

  • May 2022 - Present

  Wrote System Verilog RTL for Intel Stratix 10 FPGA to connect modules to 100G Ethernet IP for next generation computing architecture. Simulated with Xcelium. Synthesized and ran static timing analysis with Intel Quartus Prime. Wrote System Verilog RTL for Intel Stratix 10 FPGA to connect modules to 100G Ethernet IP for next generation computing architecture. Simulated with Xcelium. Synthesized and ran static timing analysis with Intel Quartus Prime.



L3Harris Technologies

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• Senior FPGA Design Engineer

  • Sep 2021 - Apr 2022

  Designed logic components for FPGA-based Telemetry Unit for Exploration Upper Stage (EUS) of NASA’s Space Launch System (SLS): Wrote VHDL RTL, simulated with ModelSim, synthesized with Synplify Pro, modeled design with Matlab. Used Jira for Agile Project Management, Story, and Task Tracking, used Crucible for design reviews Designed logic components for FPGA-based Telemetry Unit for Exploration Upper Stage (EUS) of NASA’s Space Launch System (SLS): Wrote VHDL RTL, simulated with ModelSim, synthesized with Synplify Pro, modeled design with Matlab. Used Jira for Agile Project Management, Story, and Task Tracking, used Crucible for design reviews



CPR Tools Inc.

• United States
• IT Services and IT Consulting
• 1 - 100 Employee

• Senior FPGA/ASIC Design Engineer

  • Apr 2013 - Aug 2021

  Designed NAND FLASH/SATA Controller FPGA and ASIC: VHDL design, simulation, Place and Route, Timing Closure Xilinx Artix-7 XC7A200T FPGA: NAND FLASH, MicroBlaze, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Intel eASIC N3XS 28nm ASIC: NAND FLASH, ARC EM4, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Performed schematic capture and board layout of SSD, performed lab debug and testing, NAND/SATA debugging Designed Xilinx Kintex UltraScale FPGA to control hard drive… Show more Designed NAND FLASH/SATA Controller FPGA and ASIC: VHDL design, simulation, Place and Route, Timing Closure Xilinx Artix-7 XC7A200T FPGA: NAND FLASH, MicroBlaze, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Intel eASIC N3XS 28nm ASIC: NAND FLASH, ARC EM4, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Performed schematic capture and board layout of SSD, performed lab debug and testing, NAND/SATA debugging Designed Xilinx Kintex UltraScale FPGA to control hard drive spindle and read head Performed circuit prototyping of spinning hard drive spindle controller, head controller, and differential probe Show less Designed NAND FLASH/SATA Controller FPGA and ASIC: VHDL design, simulation, Place and Route, Timing Closure Xilinx Artix-7 XC7A200T FPGA: NAND FLASH, MicroBlaze, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Intel eASIC N3XS 28nm ASIC: NAND FLASH, ARC EM4, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Performed schematic capture and board layout of SSD, performed lab debug and testing, NAND/SATA debugging Designed Xilinx Kintex UltraScale FPGA to control hard drive… Show more Designed NAND FLASH/SATA Controller FPGA and ASIC: VHDL design, simulation, Place and Route, Timing Closure Xilinx Artix-7 XC7A200T FPGA: NAND FLASH, MicroBlaze, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Intel eASIC N3XS 28nm ASIC: NAND FLASH, ARC EM4, DDR4, SATA, PCIe, SPI, I2C, FRAM, Encryption Performed schematic capture and board layout of SSD, performed lab debug and testing, NAND/SATA debugging Designed Xilinx Kintex UltraScale FPGA to control hard drive spindle and read head Performed circuit prototyping of spinning hard drive spindle controller, head controller, and differential probe Show less



Westinghouse Electric Company

• Nuclear Electric Power Generation
• 700 & Above Employee

• Principal FPGA Design Engineer

  • Jul 2011 - Mar 2013

  Successfully lead a team of FPGA design engineers to design highly-complex and highly-reliable FPGAs. FPGAs performed functions such as math calculations on thermocouples/RTDs, voltage/current detection/generation, control of input/output channels, access to Non-Volatile Memories, and custom logic for Nuclear Power Plant Safety Systems Successfully lead a team of FPGA design engineers to design highly-complex and highly-reliable FPGAs. FPGAs performed functions such as math calculations on thermocouples/RTDs, voltage/current detection/generation, control of input/output channels, access to Non-Volatile Memories, and custom logic for Nuclear Power Plant Safety Systems



Ansaldo STS A Hitachi Group Company

• Italy
• Truck Transportation
• 700 & Above Employee

• Senior Hardware Engineer

  • Jan 2011 - Jul 2011

  Lead the design of 2 Xilinx/Altera FPGAs to perform DSP/FFT analysis on analog/digital signals ranging from DC to 60 Hz. Lead the design of 2 Xilinx/Altera FPGAs to perform DSP/FFT analysis on analog/digital signals ranging from DC to 60 Hz.



ECI Telecom

• United States
• Telecommunications
• 700 & Above Employee

• Lead Hardware Engineer

  • May 2009 - Jan 2011

  Designed and simulated logic to implement Bi-Directional Forward Detection in a next generation 10G network card. Wrote VHDL RTL running at 200MHz, synthesized and performed Place and Route using Altera Quartus tool. Designed and simulated logic to implement Bi-Directional Forward Detection in a next generation 10G network card. Wrote VHDL RTL running at 200MHz, synthesized and performed Place and Route using Altera Quartus tool.



Ericsson

• Sweden
• Telecommunications
• 700 & Above Employee

• Lead Hardware Design Engineer

  • Jan 2005 - May 2009

  Aided in the design of a Xilinx Vertex 5 FX130T, SPI4.2 to 6.25G Serial Link Buffering and Scheduling FPGA in next-generation router. Designed ingress buffer memory controller and integrated vendor SPI4.2 cores in FPGA. Wrote Verilog RTL running at 200MHz, synthesized using Synplify Pro, and pipelined logic to meet timing. Simulated design using Synopsys VCS/DVE and Synopsys VMM Methodology.

• Lead Hardware Design Engineer

  • 2000 - 2005

  Lead design team of 4 engineers to implement requirements, perform VHDL RTL design, and run simulations. Aided in architecture definition, VHDL RTL coded, simulated using Modelsim, synthesized using Altera Quartus tool, defined pinouts, defined timing constraints, floorplanned, and met timing for four highly-complex FPGAs: Co-Led OC-48/192c Packet/Cell Fabric ASIC (5 Million gate IBM 0.18 micron standard cell). VHDL RTL designed, simulated using Modelsim, synthesized and debugged 125 MHz… Show more Lead design team of 4 engineers to implement requirements, perform VHDL RTL design, and run simulations. Aided in architecture definition, VHDL RTL coded, simulated using Modelsim, synthesized using Altera Quartus tool, defined pinouts, defined timing constraints, floorplanned, and met timing for four highly-complex FPGAs: Co-Led OC-48/192c Packet/Cell Fabric ASIC (5 Million gate IBM 0.18 micron standard cell). VHDL RTL designed, simulated using Modelsim, synthesized and debugged 125 MHz Backplane Synchronization logic in Ingress Fabric ASIC for 480G Packet/Cell switch. Led synthesis and static timing analysis of ASIC with Synopsys DC. First pass success



FORE Systems

• Computer Networking Products
• 1 - 100 Employee

• Hardware Design Engineer

  • 1995 - 2000

  OC-12 Port Card ASIC (1 Million gate 0.25 micron standard cell): Successfully designed and simulated 80 MHz Buffer Read and Connection Setup logic in ASIC for 40G ATM Cell Switch. VHDL RTL designed, simulated with Modelsim, synthesized and timing analyzed with Synopsys, and inserted full scan. OC-3 SONET PHY ASIC (78,000 gate 0.5 micron standard cell): Verified ASIC functionality against SONET specifications. Aided in specification, design, and simulation of Clock Recovery Unit(CRU) and… Show more OC-12 Port Card ASIC (1 Million gate 0.25 micron standard cell): Successfully designed and simulated 80 MHz Buffer Read and Connection Setup logic in ASIC for 40G ATM Cell Switch. VHDL RTL designed, simulated with Modelsim, synthesized and timing analyzed with Synopsys, and inserted full scan. OC-3 SONET PHY ASIC (78,000 gate 0.5 micron standard cell): Verified ASIC functionality against SONET specifications. Aided in specification, design, and simulation of Clock Recovery Unit(CRU) and aided in synthesis with Synopsys Show less OC-12 Port Card ASIC (1 Million gate 0.25 micron standard cell): Successfully designed and simulated 80 MHz Buffer Read and Connection Setup logic in ASIC for 40G ATM Cell Switch. VHDL RTL designed, simulated with Modelsim, synthesized and timing analyzed with Synopsys, and inserted full scan. OC-3 SONET PHY ASIC (78,000 gate 0.5 micron standard cell): Verified ASIC functionality against SONET specifications. Aided in specification, design, and simulation of Clock Recovery Unit(CRU) and… Show more OC-12 Port Card ASIC (1 Million gate 0.25 micron standard cell): Successfully designed and simulated 80 MHz Buffer Read and Connection Setup logic in ASIC for 40G ATM Cell Switch. VHDL RTL designed, simulated with Modelsim, synthesized and timing analyzed with Synopsys, and inserted full scan. OC-3 SONET PHY ASIC (78,000 gate 0.5 micron standard cell): Verified ASIC functionality against SONET specifications. Aided in specification, design, and simulation of Clock Recovery Unit(CRU) and aided in synthesis with Synopsys Show less