Giacomo Sarasin

Analog & Mixed Signal IC Layout Engineer at Canova Tech
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Contact Information
us****@****om
(386) 825-5501
Location
Mestrino, Veneto, Italy, IT
Languages
  • Inglese Full professional proficiency
  • Italiano Native or bilingual proficiency

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Bio

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Credentials

  • Functional Safety Engineer
    TÜV SÜD
    Jun, 2020
    - Nov, 2024
  • First Certificate in English - B2
    University of Cambridge
    Jun, 2012
    - Nov, 2024

Experience

  • Canova Tech
    • Italy
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Analog & Mixed Signal IC Layout Engineer
      • Mar 2021 - Present

  • Fiamm Energy Technology
    • Italy
    • Motor Vehicle Manufacturing
    • 400 - 500 Employee
    • R&D Electronic Engineer
      • Sep 2019 - Mar 2021

  • Infineon Technologies
    • Germany
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Internship Trainee - Analog and mixed signal IC design
      • Oct 2018 - Jul 2019

Education

  • Università degli Studi di Padova
    Laurea Magistrale LM, Ingegneria Elettronica
    2016 - 2019
  • Università degli Studi di Padova
    Laurea triennale, Ingegneria dell'Informazione
    2013 - 2016

Community

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