Gaurav G.

Manager Design and Emulation at IFCS Technologies Private Limited
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Contact Information
us****@****om
(386) 825-5501
Location
Bengaluru, Karnataka, India, IN

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Experience

  • IFCS Technologies Private Limited
    • India
    • Semiconductors
    • 1 - 100 Employee
    • Manager Design and Emulation
      • Jan 2019 - Present

      Ramp up Emulation Teams for : - Port Full chipSoC onto the Palladium - Identify the structural changes to the placement of the design while porting. - Carve out Patches , emulation memory , blackboxes, PHY identification and substitution - Automation of the same for RTL updates and continuous releases. - Debug transactions(Processor-Peripheral programming and functionality) on emulation Platform - Regression Infrastructure creation Ramp up Emulation Teams for : - Port Full chipSoC onto the Palladium - Identify the structural changes to the placement of the design while porting. - Carve out Patches , emulation memory , blackboxes, PHY identification and substitution - Automation of the same for RTL updates and continuous releases. - Debug transactions(Processor-Peripheral programming and functionality) on emulation Platform - Regression Infrastructure creation

  • Sivaltech
    • United States
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Technical Manager RTL Design and Emulation
      • Mar 2017 - Present

  • Intel Corporation
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • SMTS
      • Apr 2013 - Jan 2016

      Emulation of Mobile And Networking Chipset on Palladium. Emulation of Mobile And Networking Chipset on Palladium.

  • Texas Instruments
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Sr Design Engineer
      • Mar 2009 - Dec 2012

      Chip Lead from Ultra Low Power Mixed Signal Processors Chip Lead from Ultra Low Power Mixed Signal Processors

  • ARM Embedded Technologies Private Ltd.
    • India
    • Business Consulting and Services
    • 1 - 100 Employee
    • Sr IP Design engineer
      • 2007 - 2010

      IP design of DDR IPs IP design of DDR IPs

  • Cadence Design Systems
    • United States
    • Software Development
    • 700 & Above Employee
    • Software Engineer
      • Mar 2006 - May 2008

      RTL transactions IP , Emulation Platform Palladium II validation RTL transactions IP , Emulation Platform Palladium II validation

Education

  • Dhirubhai Ambani Institute of Information and Communication Technology
    B.tech, Vlsi
    2001 - 2005

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