Eric Rentschler
Fellow and Chief Validation Engineer at Woodpecker Semiconductor- Claim this Profile
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Bio
jeff rearick
Eric is a technical expert in Design-For-Debug (DFD) and Design-For-Validation (DFV) and is the primary architect of AMD's DFD/DFV strategy. He has personally done much of the hands-on design, verification, and implementation of AMD's on-chip debug circuitry and worked closely with the software team to build a highly productive debugging tool set to utilize these features. He is an exceptionally good driver of cross-organizational progress and works well with external customers, spanning the spectrum from high-level executive engagements to working out technical details with the guys in the trenches. He keeps his team motivated and focused and leads by example as well as anyone with whom I've ever worked.
jeff rearick
Eric is a technical expert in Design-For-Debug (DFD) and Design-For-Validation (DFV) and is the primary architect of AMD's DFD/DFV strategy. He has personally done much of the hands-on design, verification, and implementation of AMD's on-chip debug circuitry and worked closely with the software team to build a highly productive debugging tool set to utilize these features. He is an exceptionally good driver of cross-organizational progress and works well with external customers, spanning the spectrum from high-level executive engagements to working out technical details with the guys in the trenches. He keeps his team motivated and focused and leads by example as well as anyone with whom I've ever worked.
jeff rearick
Eric is a technical expert in Design-For-Debug (DFD) and Design-For-Validation (DFV) and is the primary architect of AMD's DFD/DFV strategy. He has personally done much of the hands-on design, verification, and implementation of AMD's on-chip debug circuitry and worked closely with the software team to build a highly productive debugging tool set to utilize these features. He is an exceptionally good driver of cross-organizational progress and works well with external customers, spanning the spectrum from high-level executive engagements to working out technical details with the guys in the trenches. He keeps his team motivated and focused and leads by example as well as anyone with whom I've ever worked.
jeff rearick
Eric is a technical expert in Design-For-Debug (DFD) and Design-For-Validation (DFV) and is the primary architect of AMD's DFD/DFV strategy. He has personally done much of the hands-on design, verification, and implementation of AMD's on-chip debug circuitry and worked closely with the software team to build a highly productive debugging tool set to utilize these features. He is an exceptionally good driver of cross-organizational progress and works well with external customers, spanning the spectrum from high-level executive engagements to working out technical details with the guys in the trenches. He keeps his team motivated and focused and leads by example as well as anyone with whom I've ever worked.
Experience
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Woodpecker Semiconductor
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Singapore
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Semiconductor Manufacturing
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1 - 100 Employee
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Fellow and Chief Validation Engineer
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Sep 2022 - Present
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Mentor Graphics
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Canada
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Software Development
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1 - 100 Employee
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Chief Validation Scientist
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May 2014 - Sep 2022
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AMD
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France
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Architecture and Planning
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1 - 100 Employee
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Fellow
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Apr 2006 - Apr 2014
Architected and drove powerful new debug and validation features across AMD roadmap resulting in immediate time-to-market savings as well as lasting transformational change across the culture. The first round of products demonstrated a 2x reduction in debug time across server and APU products. Collaborated to drive change across worldwide geographies effecting entire product roadmap in hardware, microcode, SW to reduce debug and validation cycles, improve power and performance analysis. Saved entire silicon spins and months of time-to-market on complex new SoCs. AMD Spirit of Success Award for effectiveness of Design for Debug and Validation Features 1H, 2010 Show less
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DPSP
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United States
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Medical Practices
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Patroller
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1994 - 2009
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Intel Corporation
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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Senior Engineer
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Jan 2005 - Apr 2006
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Hewlett Packard
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United States
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Information Technology & Services
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300 - 400 Employee
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Engineer
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1989 - 2005
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Engineer
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1989 - 2005
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Education
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1987 - 1989
University of Michigan
BS, Electrical Engineering -
1983 - 1986
Bowling Green State University
Bachelors of Science, Electronic Technology
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