EranCohen eranNineNineAtComcastDotNet
Distinguished Engineer (VLSI, FPGA, ASIC, DSP) at Lassen Peak- Claim this Profile
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Bio
Jerry Corcoran
Eran did a great job for us. Very solid, did a great job, worked well with the team, solved some difficult problems. Would definitely recommend
Rajagopalan G K
Eran is a sharp technical manager with a great work ethic. I enjoyed working with him and our team benefited greatly from his attention to detail. I trust him to deliver on any project related to VLSI, SoCs, DSPs and FPGAs including low power products.
Jerry Corcoran
Eran did a great job for us. Very solid, did a great job, worked well with the team, solved some difficult problems. Would definitely recommend
Rajagopalan G K
Eran is a sharp technical manager with a great work ethic. I enjoyed working with him and our team benefited greatly from his attention to detail. I trust him to deliver on any project related to VLSI, SoCs, DSPs and FPGAs including low power products.
Jerry Corcoran
Eran did a great job for us. Very solid, did a great job, worked well with the team, solved some difficult problems. Would definitely recommend
Rajagopalan G K
Eran is a sharp technical manager with a great work ethic. I enjoyed working with him and our team benefited greatly from his attention to detail. I trust him to deliver on any project related to VLSI, SoCs, DSPs and FPGAs including low power products.
Jerry Corcoran
Eran did a great job for us. Very solid, did a great job, worked well with the team, solved some difficult problems. Would definitely recommend
Rajagopalan G K
Eran is a sharp technical manager with a great work ethic. I enjoyed working with him and our team benefited greatly from his attention to detail. I trust him to deliver on any project related to VLSI, SoCs, DSPs and FPGAs including low power products.
Experience
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Lassen Peak
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United States
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Public Safety
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1 - 100 Employee
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Distinguished Engineer (VLSI, FPGA, ASIC, DSP)
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Jul 2023 - Present
Micro architecture, Design, integration, and testing of DSP block chain for a short range radar. Micro architecture, Design, integration, and testing of DSP block chain for a short range radar.
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NFTI Corporation
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Cupertino
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ASIC and FPGA (RTL, Verilog) expert developer
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Jan 1995 - Jul 2023
Highly skilled expert with 30 years of leadership and hands on experience developing ASICs and FPGAs throughout the entire flow: Architecture and specification, micro-architecture, design (RTL, Verilog and VHDL), debug, verification, DFT, synthesis and timing closure, formal verification, prototyping and emulation, interfacing with physical design (back end) groups, COT and foundry service providers, and silicon bring up and interfacing with hardware, software and application groups. Led or participated in the design of dozens of ASICs, mainly in the area of wired and wireless physical Layer communications and DSP, but also in image and video processing, compression and coding, low power consumer application, CPUs and more. Worked in diverse groups and environments for big and established companies, as well as numerous startup companies. Broad and deep knowledge of most (if not all) industry standard tools and flows. Driven self starter individual, fast learner, team player, experienced in building groups and companies from the ground up. Show less
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Google
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United States
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Software Development
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700 & Above Employee
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Sr. Silicon Engineer
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Jul 2021 - Mar 2023
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Esencia Technologies Inc.
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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Distinguished Engineer
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Apr 2018 - Jul 2020
• Led the front end developing (Design and Verification) of a Computer Vision IP for Facebook's Oculus division for a 7nm ASIC. • Designed several of the DSP blocs of the above design, including debug, CDC, Lint, development of test plan and functional simulation and code coverage. • Participated in developing PCIE (GEN 5/4/3) and CXL IP for Intel’s (Formerly Altera) Agilex FPGA, including design, test bench and tests development, Linting, CDC, Synthesis, scripting and timing optimization. • Led the front end developing (Design and Verification) of a Computer Vision IP for Facebook's Oculus division for a 7nm ASIC. • Designed several of the DSP blocs of the above design, including debug, CDC, Lint, development of test plan and functional simulation and code coverage. • Participated in developing PCIE (GEN 5/4/3) and CXL IP for Intel’s (Formerly Altera) Agilex FPGA, including design, test bench and tests development, Linting, CDC, Synthesis, scripting and timing optimization.
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Aeva Inc.
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Mountain View, California, United States
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FPGA and ASIC RTL Developer/Consultant
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Feb 2019 - Apr 2020
Developed numerous DSP blocks and subsystems such as FFT, IFFT, phase corrections, Filters, Interpolators, Mixers, and many others for FPGAs and ASICs for an advanced high performance autonomous driving navigation system. Developed numerous DSP blocks and subsystems such as FFT, IFFT, phase corrections, Filters, Interpolators, Mixers, and many others for FPGAs and ASICs for an advanced high performance autonomous driving navigation system.
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NVXL Technology, Inc.
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United States
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Computer Hardware Manufacturing
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RTL developer (Consultant)
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Jun 2017 - Apr 2018
- Developed high performance RTL modules and subsystems for CNN and DNN based deep machine learning ASICs and FPGAs. - Developed high performance RTL modules and subsystems for CNN and DNN based deep machine learning ASICs and FPGAs.
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Cadence Design Systems
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San Jose, CA
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FPGA developer (Consultant)
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Jun 2016 - Jun 2017
Developing and maintain IP blocks and interfaces for the FPGAs for a emulation and prototype systems. The FPGAs being used are the latest biggest and fastest that exist. Developing and maintain IP blocks and interfaces for the FPGAs for a emulation and prototype systems. The FPGAs being used are the latest biggest and fastest that exist.
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Samsung Semi Conductor (Display Labs)
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San Jose, CA
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RTL developer (Consultant)
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Aug 2015 - Jun 2016
- Developed a transmitter and a received for a very high speed video communication protocol (Taegetted at big 4k/8k TV screens) for FPGA and ASIC. - Scoped out HDMI2.1 project, and developed initial architecture. - Developed a transmitter and a received for a very high speed video communication protocol (Taegetted at big 4k/8k TV screens) for FPGA and ASIC. - Scoped out HDMI2.1 project, and developed initial architecture.
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MSPT LLC
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1820 Hackett Ave Mountain View, CA 94043
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FPGA developer (Consultant)
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Jul 2014 - Sep 2015
- Ported an x-ray scanner controller from an obsolete implementation based on an old FPGA and DSP into a new state of the art Altera FPGA device, and added some new features. - Participated in debug and integration with an Arm processor (HW and SW), ADC, motor, LED, and various other sophisticated devices. - Ported an x-ray scanner controller from an obsolete implementation based on an old FPGA and DSP into a new state of the art Altera FPGA device, and added some new features. - Participated in debug and integration with an Arm processor (HW and SW), ADC, motor, LED, and various other sophisticated devices.
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NGCodec
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United States
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Semiconductor Manufacturing
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FPGA consultant
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Jul 2015 - Aug 2015
Helped developing an FPGA infrastructure for an H.265 video Encoder/Decoder IP. Helped developing an FPGA infrastructure for an H.265 video Encoder/Decoder IP.
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SA Photonics, a CACI Company
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United States
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Defense and Space Manufacturing
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1 - 100 Employee
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FPGA developer (Consultant)
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Mar 2015 - Jul 2015
Redesigned a satellite optical Modem on a Zynq FPGA, and made it to work. Implement a very high speed data aquisition system on a xilinx FPGA. Redesigned a satellite optical Modem on a Zynq FPGA, and made it to work. Implement a very high speed data aquisition system on a xilinx FPGA.
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Kumu Networks
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United States
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Telecommunications
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1 - 100 Employee
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FPGA/DSP developer (Consultant)
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Oct 2014 - Mar 2015
- Implemented several heavy duty DSP blocks for a full duplex wireless communication system. The design was pushing the envelope in terms of speed and complexity. - Helped the team complete a working demo for MWC in March/2014, through a very focused and intensive effort in a very short time. - Implemented several heavy duty DSP blocks for a full duplex wireless communication system. The design was pushing the envelope in terms of speed and complexity. - Helped the team complete a working demo for MWC in March/2014, through a very focused and intensive effort in a very short time.
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Peraso Inc.
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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ASIC Design Engineer (Consultant)
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May 2013 - Oct 2014
Architect and Develop a Reed Solomon based FEC (Encoder and Decoder) for 100Gb Ethernet ASIC using (TSMC 28nM). Implement interface blocks such SPI, I2C, MDIO, JTAG, GPIO etc. Participate in development of other blocks and functions as needed, integration, verification, synthesis, Lint, and so on. Architect and Develop a Reed Solomon based FEC (Encoder and Decoder) for 100Gb Ethernet ASIC using (TSMC 28nM). Implement interface blocks such SPI, I2C, MDIO, JTAG, GPIO etc. Participate in development of other blocks and functions as needed, integration, verification, synthesis, Lint, and so on.
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Echelon
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San Jose, CA
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FPGA and ASIC developer (Consultant)
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Nov 2011 - Jul 2013
- Architected, Designed and verified (Including developing Matlab/Octave models) several DSP oriented blocks (such as CIC Interpolator, CIC Decimator) for a Power line Modem based on a Simulink models. - RTL was developed in such a way that it could be used on an FPGA prototype as well as ASIC. - Architected, Designed and verified (Including developing Matlab/Octave models) several DSP oriented blocks (such as CIC Interpolator, CIC Decimator) for a Power line Modem based on a Simulink models. - RTL was developed in such a way that it could be used on an FPGA prototype as well as ASIC.
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Texas Instruments
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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ASIC and FPGA consultant
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Feb 2007 - Jun 2013
- Designed, verified and synthesized several generations of CFR (Crest Factor Reduction) block and a DPD (Digital PreDistortion) blocks for a wireless infrastructure ASSP. Both blocks are about 3M gates together, and made about ½ of the ASIC. Lots of attention was given to low power. Both blocks were highly complex. - Ported and emulated a JESD design on FPGA platform. - Designed misc blocks and functions such as asynchronous FIFO, Interpolation filters, digital mixers,modulators, AGC, and more. - Ran Formal Verification, Lint and gate level simulations for the complete ASICs as well as block level. - Ported and emulated a JESD design on FPGA platform. - Participated in designing a UWB (Wireless USB). Implemented various DSP blocks such as Viterbi Decoder,OFDM Mapper, Packet Detector, and several other such blocks.. - Participated in developing configuration SW for the above ASICs. Show less
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Samplify Systems
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Santa Clara, CA
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VLSI/RTL developer (ASIC and FPGA) (Consultant)
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Dec 2011 - Apr 2013
Developed various computational and control blocks for a highly programmable low latency proprietary compression/Decompression FPGA, including micro-architecture, Design and verification. Developed test bench and test suite, and a set of debug and regression scripts for the whole system. Developed the top level module of the system, the synthesis scripts, and managed FPGA resources and timing. Developed various computational and control blocks for a highly programmable low latency proprietary compression/Decompression FPGA, including micro-architecture, Design and verification. Developed test bench and test suite, and a set of debug and regression scripts for the whole system. Developed the top level module of the system, the synthesis scripts, and managed FPGA resources and timing.
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Intevac
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United States
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Semiconductor Manufacturing
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100 - 200 Employee
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Lead FPGA Engineer/Consultant
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2010 - 2010
- FPGA logic design lead for a high resolution high performance night vision camera. - Designed several image processing, interface and control blocks such as sensor controller, I2C, SPI, DDR controller, Gamma, AGC, and more. - FPGA logic design lead for a high resolution high performance night vision camera. - Designed several image processing, interface and control blocks such as sensor controller, I2C, SPI, DDR controller, Gamma, AGC, and more.
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Lecroy (Later aquired by Teledyne)
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Santa Clara, CA
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ASIC Design Engineer (Consultant)
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Oct 2007 - Oct 2008
- Modified and integrated Bluetooth Physical layer module from Broadcom into Bluetooth protocol analyzer by Lecroy. - Modified and integrated Bluetooth Physical layer module from Broadcom into Bluetooth protocol analyzer by Lecroy.
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Ipsil Inc
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United States
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Business Consulting and Services
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RTL developer (Consultant)
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Jul 2006 - Aug 2007
Developed TCP/IP stack in hardware and implemented on an FPGA. Integrated the TCP/IP into clients' products. Developed TCP/IP stack in hardware and implemented on an FPGA. Integrated the TCP/IP into clients' products.
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Broadcom
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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ASIC development consultant
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2006 - 2006
- Designed numerous audio filters for a Bluetooth-audio ASIC. - Integrated Bluetooth Physical layer into Bluetooth protocol analyzer. - Designed numerous audio filters for a Bluetooth-audio ASIC. - Integrated Bluetooth Physical layer into Bluetooth protocol analyzer.
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VP of Hardware
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2006 - 2006
Architected and designed the hardware for an EDA tool that applies dynamic data driven clock gating to any design. This is on top of static application of clock gating that is done by most synthesis EDA tools. The technology was acquired my Magma Design automation. Architected and designed the hardware for an EDA tool that applies dynamic data driven clock gating to any design. This is on top of static application of clock gating that is done by most synthesis EDA tools. The technology was acquired my Magma Design automation.
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Ambarella Inc
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United States
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Semiconductor Manufacturing
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300 - 400 Employee
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H264/JPEG transformation Verification Consultant
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2004 - 2006
- Developed test plan and executed the verification of major data processing blocks for 2 generations of an H.264/MPEG/JPEG Encoder/Decoder ASIC. - Developed test plan and executed the verification of major data processing blocks for 2 generations of an H.264/MPEG/JPEG Encoder/Decoder ASIC.
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ASIC/FPGA Consultant
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2003 - 2006
- Participated in the development of a low power digital power supply controller/regulator for embedded systems. - Emulated the above described ASICs on FPGA platforms. - Participated in the development of a low power digital power supply controller/regulator for embedded systems. - Emulated the above described ASICs on FPGA platforms.
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Intel Corporation
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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ASIC Consultant
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2005 - 2005
Analyzed various technologies and IP acquired by Intel and developed recommendations of how to use it in various Open Cable and other ASICs. Analyzed various technologies and IP acquired by Intel and developed recommendations of how to use it in various Open Cable and other ASICs.
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Teranetics
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Semiconductor Manufacturing
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1 - 100 Employee
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VP of IC Engineering
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2002 - 2004
• Building and running the mixed signal, IT, digital and backend teams. • Architectuing the digital chip, which is DSP heavy with tens of millions of gates at high speeds, yet low power. • Participating hands on in the digital chip, board and FPGA design. • Exploring potential IP cores and SOC modules to be used on the digital and analog chips. • Participating in developing the system concept and architecture, standard committee activities, etc. • Building and running the mixed signal, IT, digital and backend teams. • Architectuing the digital chip, which is DSP heavy with tens of millions of gates at high speeds, yet low power. • Participating hands on in the digital chip, board and FPGA design. • Exploring potential IP cores and SOC modules to be used on the digital and analog chips. • Participating in developing the system concept and architecture, standard committee activities, etc.
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Investor
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2000 - 2004
Private investor and unofficial advisor. Private investor and unofficial advisor.
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Sr. Director of VLSI
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2000 - 2001
• Built and led the VLSI group that peaked at ~30 top notch engineers. The VLSI group deals with architecture, design, verification, synthesis, testing and bring up of large and complex deep sub micron wireless processors. • Supervised the development of a 14M gate, >200MHz multi channel basbeband processing chip for 3G cellular base stations. Two stages of the chip were taped out and resulted with fully functional silicon in less than a year. • Greatly improved the cooperation and coerced tight interaction between VLSI and the other group: Marketing, SW, HW, Systems, and COT/Physical Design (floor plan, static timing, place and route). • Defined, improved and evaluated procedures, methodology, design flow and tool set for the VLSI group that included random verification (using Vera), formal verification (Assertion and equivalency checking), code coverage, co-simulation, coding rules and linting, emulation, etc. • Contributed to the architecture of these chips, and enhanced BIST, scan, and DFT in general. Show less
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PCTEL
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United States
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Telecommunications
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100 - 200 Employee
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Director of Broadband HW
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1998 - 2001
• Architected and Implemented (hands on, almost by myself) a combination ADSL/V.92 modem HW (FPGA prototyping, production ASIC and various PCI reference boards). The design included FFT, IFFT, interpolation IIR, Codec interface, etc. • Wrote and maintained the functional and detailed specification for the ASICs mentioned above. • Built FPGA prototypes (Xilinx Virtex and Virtex-II) of the above ASIC. • Built from the ground up, and managed the Broadband HW team in PC-Tel. • Represented the company in the ACR (Advanced Communications Riser) HW specification development. • Participated in the product and system definition of various broadband products in the company. Show less
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Sr. ASIC manager, Architect
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1994 - 1998
• First engineer to join Terayon. Built a 15 engineer ASIC team from the ground up, and developed its design and verification methodologies and processes. Terayon employs ~700 people today.• Participated in developing the system concept and specification, including technical interaction with customers. Contributed significantly to the system definition: Algorithms, Software, Hardware and RF.• Architected an ASIC that implements most of the cable modem mentioned above, and led its development from concept to production. The chip had 525,000 gates (mostly logic) in more than 50 different blocks, including FEC (Reed-Solomon, Trellis, Viterbi), sophisticated modulation such as CAP, QAM, S-CDMA (DOCSIS 2.0) and other DSP intensive blocks (FIR, raised cosine shaping filters, matched filter, Decimation, Interpolation, Carrier and clock recovery,AGC, noise prediction adaptive equalizers, precoder, and more).• Developed road map and detailed architecture and wrote specifications for Terayon’s other ASICs, responsible for methodology and development process, relationship with ASIC vendors, packaging and testability.• Millions of chips have been sold so far, and still going strongly. This chip virtually took Terayon public. Show less
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ASIC manager, ASIC architect
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1994 - 1998
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Lead VLSI engineer
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1992 - 1994
Lead Senior VLSI Engineer • Architected, designed and implemented the Signal Processing Engine, which was the heart of one of the most successful xDSL modem chip sets ever built. That department was later spun off as Globe Span. • Conducted DSP simulations and LAN modeling, and led the system engineering for a fast transceiver for LAN applications (100/10Mbps Ethernet, FDDI, and ATM in different rates). • Definition and design of a chip-set that implements fast Ethernet transceiver (100/10Mbps). ). The chip included cross-coupled echo canceller, adaptive blind equalizer, etc. • Participated in IEEE 802.3 standards committee and its High Speed Working Group. • Filed two patent applications regarding the implementation of the above fast transceiver. Show less
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National Semiconductor
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Semiconductor Manufacturing
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400 - 500 Employee
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VLSI Engineer
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1986 - 1992
• Implemented a V.32bis modem transmitter and echo canceler, based on National Semi Conductor DSP. • Participated in the development of different CISC and DSP processors (up to 4 million transistors). • Played a key role in the automation and systematization of the design and verification process. • Implemented a V.32bis modem transmitter and echo canceler, based on National Semi Conductor DSP. • Participated in the development of different CISC and DSP processors (up to 4 million transistors). • Played a key role in the automation and systematization of the design and verification process.
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Education
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Technion - Israel Institute of Technology
MSEE, VLSI, DSP -
Technion - Israel Institute of Technology
BSCS, Communications, Computer architectures