Experience

Analog Bits

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Circuit Design Engineer

  • Jan 2013 - Present

  • Designed SerDes Tx integer-N PLLs from 14nm to 45nm processes. -- PLLs met multiple protocols, including: PCIe Gen 4, SATA Gen 3, XFI, SGMII, customer specific, etc. -- Random Jitter 0.5 to 2 ps-RMS depending on the protocol, power, and area requirements. -- Refined behavioral model to optimize development time efficiently. -- Designed and characterized VCOs, charge pumps, dividers, and clock distribution networks. • Designed SerDes Rx CDR from 14nm to 45nm processes. -- Met jitter tolerance specs, passed BER requirements. -- Project lead for several product releases. -- Aided junior engineers with guidance and instruction. -- Responsible for customer releases of databases, datasheets, and other deliverables. -- Guided layout for optimal circuit performance. Show less



UCLA

• United States
• Higher Education
• 700 & Above Employee

• Teaching Assistant

  • Sep 2011 - Dec 2012

  • Led weekly discussions. • Held multiple lectures under the supervision of the professor. • Assisted with course logistics: grading, test creation, office hours, homework assignments, etc. • Led weekly discussions. • Held multiple lectures under the supervision of the professor. • Assisted with course logistics: grading, test creation, office hours, homework assignments, etc.



Spansion is Cypress Semiconductor

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Product Development Engineer

  • Jul 2005 - Aug 2010

  • Characterized flash memory devices from first silicon to customer approved samples. -- Tested data sheet parameters for program, erase, and synchronous/asynchronous reads. -- Enhanced device performance by analysis of VT distributions, gm analysis, and sense amp margins. • Qualified 90nm and 65nm products for wireless products. -- Focused on erase suspend qualification and power-on schemes. -- Analyzed failures related to walk-out bits, data retention, and inadvertent programming. • Executed improvements for production and manufacturing level devices. -- Made yield enhancements and test-time reductions. -- Managed test flows which determined marketable units for customers. Show less