Experience

Fitipower Integrated Technology Inc.

• Taiwan
• Semiconductors
• 1 - 100 Employee

• 資深經理

  • Sep 2021 - Present

  1. In charge of DDR5 PMIC product development, from spec to tape out 2. BLDC mcu(Cortex-M0+) controller development - Communicate with SA/analog RD for design implementation spec - Architecture/function block define & RTL coding - Digital front design flow: DC/STA/ATPG/LEC - Verilog_A behavior model support for analog RD - Simulation testbench & environment building from scratch - Simulation/FPGA verification & debug 1. In charge of DDR5 PMIC product development, from spec to tape out 2. BLDC mcu(Cortex-M0+) controller development - Communicate with SA/analog RD for design implementation spec - Architecture/function block define & RTL coding - Digital front design flow: DC/STA/ATPG/LEC - Verilog_A behavior model support for analog RD - Simulation testbench & environment building from scratch - Simulation/FPGA verification & debug



Advantech

• Taiwan
• Industrial Automation
• 700 & Above Employee

• Senior Manager

  • Jul 2019 - Sep 2021

  1. In charge of FPGA team project & people management. 2. Server platform power management FPGA design/verification/maintain. 3. Video streaming/AI FPGA design/verification/maintain. 1. In charge of FPGA team project & people management. 2. Server platform power management FPGA design/verification/maintain. 3. Video streaming/AI FPGA design/verification/maintain.



VIA-Labs Inc.

• Xin-Dien New Taipei City

• Technical Manager

  • Dec 2014 - Jun 2019

  Engage & in charge of USB3.1 Hub design verification, since 2014.12. 1. Simulation environment maintain & improvement. 2. Direct USB3.1 hub verification methodology & task force. 3. Contribution to VL820/VL821(VT3518) to win the world's first USB3.1 gen-2 KGH. In charge of RUTC(routing logic controller) design tasks, since 2017.02. 1. Maintain & improve RUTC desgin for both USB3.1 gen-1 & gen-2 hub. 2. Successfully change dual port SRAM to single port SRAM of 128KB size in gen-2 upstream data path, reduce ~10% of digital logic gate count. 3. Participate gen-1 hub upstream data path architecture from per-port 1KB to 4-port share 4KB SRAM. Show less



Genesys Logic, Inc.

• Taiwan
• Semiconductors
• 1 - 100 Employee

• RD department manager, IP & Cooperative Development Division

  • Apr 2011 - Jul 2014

  • Participate and manage GLI’s plugged & serdes PHY IP development & strategy. • In charge of USB2.0/3.0 PHY test chip new process porting exploration tape out for in house product lines & customer requirement. - TSMC 0.11um/SMIC 0.11um/UMC 40nm LP. - Over 10 test chip T/O & first cut work so far. • In charge of USB2.0/3.0PHY test chip test plan & report implementation. - Compliance test & electrical test. • IP deliverables preparation for IP customers. • Related PHY IP ECO & testing support for in house product lines. Show less



Broadway system Inc

• Computers and Electronics Manufacturing

• RD Manager

  • Jun 2008 - Apr 2011

  *In charge of SD2.0 flash memory card controller ASIC engineering tasks, from RTL coding/simulation through FPGA verification to tape out. - Shuttle version with 15-bit ECC first cut worked on 2009.0430, full-mask version taped out on 2009.0725, also first cut worked and ready for production. - Another shuttle version with 60/44/28/24-bit ECC first cut worked on 2010.1030. - Developing a USB3.0 to 4-channel SD2.0 card reader project, FPGA verification & performance measurement are both good..... Finally, product line policy changed & project suspended without continous F/W support. Coordination with IP provider & partner: Baleen/HZ in China. Show less



Mentor Graphics Corporation

• Technical Marketing Manager

  • Nov 2007 - Apr 2008

  In charge of IP product pre-sales engagement and &after-sales technical support for the Pacific Rim region. Engaged & closed 2 USB2.0 IP deals on 2007.12 & 2008.01. Also providing technical support for PKU/China through 2007.12 to 2008.2. Reason to resign: MGC shut down her IP division. In charge of IP product pre-sales engagement and &after-sales technical support for the Pacific Rim region. Engaged & closed 2 USB2.0 IP deals on 2007.12 & 2008.01. Also providing technical support for PKU/China through 2007.12 to 2008.2. Reason to resign: MGC shut down her IP division.



VIA Technologies Inc

• System Platform Business Unit R&D Deputy Manager

  • Mar 2006 - Sep 2007

  *In charge of chipset south bridge whole chip STA and &ATPG flow for four 4production projects: VT3372, VT3337A, VT3337B, and VT3402. Integration & implementation of south bridge part of project VT3382, which is an K8 interfaced SoC with highly integration of NB+SB+GFX. Reason to resign: VIA gave up the chipset business for popular CPU, and re-organized. *In charge of chipset south bridge whole chip STA and &ATPG flow for four 4production projects: VT3372, VT3337A, VT3337B, and VT3402. Integration & implementation of south bridge part of project VT3382, which is an K8 interfaced SoC with highly integration of NB+SB+GFX. Reason to resign: VIA gave up the chipset business for popular CPU, and re-organized.



Essence Technologies Inc

• ASIC RD Manager

  • Sep 2004 - Jan 2006

  ASIC design manager *Developed and verified high performance DMA controller in PCI-bridge for the network security accelerator chip. *In charge of the whole chip Static Timing Analysis and& post simulation both. Reason to resign: Essence was going to transfer to be a system house then, so there would be no long ASIC jobs. ASIC design manager *Developed and verified high performance DMA controller in PCI-bridge for the network security accelerator chip. *In charge of the whole chip Static Timing Analysis and& post simulation both. Reason to resign: Essence was going to transfer to be a system house then, so there would be no long ASIC jobs.



VXIS Technologies Inc

• Project Manager

  • Mar 2004 - Sep 2004

  Developed SDRAM controller for the video decoder project featured with 3D comb filter, and verified using FPGA platform. Reason to resign: Career constrained by VXIS. Developed SDRAM controller for the video decoder project featured with 3D comb filter, and verified using FPGA platform. Reason to resign: Career constrained by VXIS.



VIA Technologies Inc

• Deputy Manager

  • Jul 1996 - Feb 2004

  In charge of desktop chipset south bridge whole chip verification. Verified over 10 production south bridge ICs. Developed simulation-based automation verification environment. Built and maintained the north bridge with south bridge integration simulation and verification environment. Implemented power consumption measurement (under simulation environment) correlation with measurement come out from system, and built the south bridge performance measurement system under simulation environment. Familiar with PCI/PATA/AC97/AZALIA/SMbus/PCI-E bus protocol, and IRQ/DMA system behavior. Reason to resign: Career constrained by VIA. Show less