Dinesh Rao
VP New Business Development at QuikFynd, Inc.- Claim this Profile
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Bio
Experience
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QuikFynd, Inc.
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United States
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Information Technology & Services
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1 - 100 Employee
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VP New Business Development
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Aug 2014 - Dec 2017
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Intel Corporation
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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Business Strategy Consultant
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Jan 2012 - Apr 2014
Phoenix, Arizona Area Provided expertise for new business units to develop key strategies and plans for success with a focus on customers, capabilities and competition. • Defined business strategies to gain market segment share in the nascent automobile Advanced Driver Assistance Systems (ADAS) segment • Led and obtained ratification for an innovative security initiative with McAfee to protect against spyware/malware • Developed business strategy for a new data sharing cloud opportunity
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General Manager Business Unit
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Jan 2007 - Dec 2011
Phoenix, Arizona Area Incubated two businesses in the storage and consumer markets. Was responsible for the P&L, business development, product and media marketing, product development and validation • Doubled business revenue year over year for three years with significant ROI • Managed a virtual team of 15 people and started a new validation team • Developed a product roadmap and successfully directed, planned and launched two very successful platforms • Knowledgeable in trends with software… Show more Incubated two businesses in the storage and consumer markets. Was responsible for the P&L, business development, product and media marketing, product development and validation • Doubled business revenue year over year for three years with significant ROI • Managed a virtual team of 15 people and started a new validation team • Developed a product roadmap and successfully directed, planned and launched two very successful platforms • Knowledgeable in trends with software define storage(SDS) and software defined infrastructure(SDI) which are altering the landscape of the server/storage industry
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Business Strategy Planning (Servers/Memory)
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Jan 2002 - Dec 2006
Phoenix Defined and managed the Intel server/memory roadmap and was instrumental in standardizing a new memory architecture in the industry: • Defined and implemented strategies and plans to introduce a new platforms and memories to the industry (FBDIMM) • Successfully coordinated with industry standard bodies and ratified collaboration agreements with companies to successfully introduce platforms with the new memory • Drove Strategic Long Range Planning directions for the memory industry
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Strategic Planning Manager
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Jan 1998 - Dec 2002
Phoenix, Arizona Area Spear headed Intel’s entrance into the embedded markets by understanding customers, developing road maps and positioning products for success. Built and led a small team in embedded Intel architecture division with the goal of achieving significant revenue growth: • Defined new road map which drove increased revenues from $300M/Year to $650M/Year. • Secured design wins with Nokia, Marconi, Siemens, Alcatel, Lucent, Motorola and a host of embedded companies. • Honed market research… Show more Spear headed Intel’s entrance into the embedded markets by understanding customers, developing road maps and positioning products for success. Built and led a small team in embedded Intel architecture division with the goal of achieving significant revenue growth: • Defined new road map which drove increased revenues from $300M/Year to $650M/Year. • Secured design wins with Nokia, Marconi, Siemens, Alcatel, Lucent, Motorola and a host of embedded companies. • Honed market research and product positioning skills and launched many successful processors
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Design Unit Manager
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Jun 1994 - Dec 1997
Phoenix, Arizona Area * Responsible for logic design for the PCI to PCI Bridge Unit and the Performance Monitoring Unit for the i960RP2 IO processor * Saved the chip from a complete stepping by making clever architectural modifications * Filed for several patents and secured a patent related to IO architecture
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Logic Design Engineer
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Jan 1992 - Jun 1994
Santa Clara * Completed architecture and design of bus controller units for Itanium and Pentium II based processors * Developed an innovative solution for designing the Processor system bus * Designed a behavioral model of the Pentium II CPU core in VHDL to enable customers to use these models to debug their platform level solutions
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Design Engineer
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Jan 1990 - Dec 1992
Santa Clara * Designed the first system based on a Multi-Chip Module at Intel based on a 486 CPU, a cache SRAM and a multi-processor cache controller • Responsibilities included the complete system design taking it all the way to production
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Education
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Michigan State University
MSEE, Electrical Engineering -
Bangalore University
Bachelor's Degree, Electrical, Electronics and Communications Engineering