Experience

SASTRA University

• Research Services
• 700 & Above Employee

• Research Scientist

  • Sep 2022 - Present



Astrome

• India
• Wireless Services
• 1 - 100 Employee

• RTL Designer

  • Aug 2022 - Sep 2022

  RTL engineer to write Verilog and System Verilog codes for wireless technologies. RTL engineer to write Verilog and System Verilog codes for wireless technologies.



SASTRA Deemed University

• Research Assistant

  • Jul 2019 - Aug 2022

• Teaching Assistant

  • Sep 2018 - Jun 2019

  I have been a co-researcher to the TATA Power SED, Bangalore project in which I have performed the following tasks. 1. Identification of entropy source for PRNG. 2. Design and verification of IEEE 754 single precision arithmetic operations unit. 3. Generation of design wrapper to integrate Microsemi FPGA with ARM Cortex A9 microprocessor. 4. Validation of PRNG keys using NIST SP 800 - 22 batteries of tests. 5. Implementation of data embedding scheme to hide the generated… Show more I have been a co-researcher to the TATA Power SED, Bangalore project in which I have performed the following tasks. 1. Identification of entropy source for PRNG. 2. Design and verification of IEEE 754 single precision arithmetic operations unit. 3. Generation of design wrapper to integrate Microsemi FPGA with ARM Cortex A9 microprocessor. 4. Validation of PRNG keys using NIST SP 800 - 22 batteries of tests. 5. Implementation of data embedding scheme to hide the generated keys. 6. Establishing multi-path routing for the secure transmission.

• Junior Research Fellow

  • Feb 2017 - Aug 2018

  I have been a JRF for the CVRDE - DRDO project in which I was responsible for the following tasks. 1. Generation of True Random Keys on Intel FPGA by exploiting clock jitters. 2. Design and implementation of concurrent AES 128 bit architecture which requires only one clock to cipher the TRNG key. 3. Establishing a Ethernet communication between FPGAs with the incorporation of SoC architecture. 4. Validation of TRNG keys using NIST SP 800 - 22 & Diehard test standards.



Raja Ramanna Centre for Advanced Technology (RRCAT)

• India
• Research
• 400 - 500 Employee

• Laser Biomedical Applications and Instrumentation Division

  • Dec 2015 - Jun 2016

  Worked as project Trainee @ PLDD section where I have done the following works. 1. Design and implementation of input peripheral interface controllers for I2C, UART & SPI using VHDL on Xilinx FPGAs. 2. Design and implementation of output peripheral interface controllers for VGA, DVI & Graphics LCD using VHDL on Xilinx FPGAs. 3. Integration of input and output peripherals on FPGA to monitor the laser bombatment. Worked as project Trainee @ PLDD section where I have done the following works. 1. Design and implementation of input peripheral interface controllers for I2C, UART & SPI using VHDL on Xilinx FPGAs. 2. Design and implementation of output peripheral interface controllers for VGA, DVI & Graphics LCD using VHDL on Xilinx FPGAs. 3. Integration of input and output peripherals on FPGA to monitor the laser bombatment.